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6 дней назад

Senior Digital Signal Processing (DSP) Firmware Engineer

Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
UK
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Senior Digital Signal Processing (DSP) Firmware Engineer (FPGA/HDL): Designing, simulating, and implementing digital signal processing firmware for space telecommunications payloads, instruments, and sensors with an accent on FPGA-based signal processing, HDL development, and space mission hardware integration. Focus on defining firmware architectures from formal requirements or blank-sheet concepts, testing VHDL/Verilog implementations, troubleshooting mission hardware and software, and extending existing products.

Location: Hybrid work from offices in Harwell–Didcot, Stevenage, or Manchester, United Kingdom

Company

hirify.global is a global space technology company developing communications satellites, Earth and space observation systems, robotics, geointelligence solutions, and space exploration infrastructure.

What you will do

  • Develop space telecommunications payloads, instruments, and sensors within a multidisciplinary engineering team.
  • Design, simulate, and implement digital signal processing algorithms for telecommunications and sensing applications.
  • Create firmware design concepts from formal interface control documents, requirements, or blank-sheet functionality requests.
  • Produce formal firmware requirements where needed and develop HDL implementations in VHDL and/or Verilog.
  • Test and troubleshoot FPGA, hardware, and software components for space missions.
  • Maintain and extend existing products.

Requirements

  • University degree in computer science, engineering, physics, or another analytical or quantitative discipline.
  • 5+ years of experience designing and implementing signal processing systems using FPGA.
  • Strong VHDL and/or Verilog coding skills.
  • Strong skills in FPGA code simulation and testing.
  • Experience with formal configuration control methods.
  • Successful candidates must complete BPSS screening, including right-to-work, nationality and immigration-status, identity, basic criminal-record, employment-history, and reference checks.

Nice to have

  • C/C++ coding for SoC cores and/or vector processors, such as Xilinx Versal FPGA AI Engines.
  • Ability to lead design teams.
  • Familiarity with 5G/LTE radio stacks.
  • Familiarity with radiation-mitigation design techniques.

Culture & Benefits

  • Hybrid work model supporting work-life balance.
  • Private healthcare, disability income protection, life insurance, pension plan, and employee assistance program.
  • Benefits are available to employees and qualified dependents.
  • Equal-opportunity workplace focused on diversity, integrity, collaboration, and inclusive problem-solving.
  • Reasonable recruitment accommodations are available upon request.

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