Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Чётко описанная graduate-позиция в продуктовой компании даёт практический опыт в AI-железе, программу развития и работу с разными командами; ограничение по праву на работу в Великобритании сужает круг тех, кому она доступна.
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Без спонсорства визыAI-инфраструктураРазвитие с практикойПонятные задачи
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Graduate Hardware Engineer 2027 (AI): Developing and validating electronic systems for AI compute platforms across hardware design and signal integrity, with an accent on analogue and digital circuits, PCB development, and high-speed interfaces. Focus on analysing PCIe, Ethernet, DDR, and timing-critical signals, comparing simulations with laboratory measurements, and taking ownership of scoped hardware designs.
Location: Bristol, UK. Applicants must already have the right to work in the UK for the full duration of the programme and must not require visa sponsorship. In-person final-stage assessments take place in early spring.
Salary: £45,000 per annum
Company
hirify.global builds next-generation AI compute platforms spanning semiconductors, software, and systems at datacenter scale, and is owned by SoftBank Group.
What you will do
Develop electronic systems for AI compute platforms across Hardware Design and Signal Integrity.
Design circuits, select components, create schematics, and work with PCB layout through review, bring-up, and validation.
Work with digital and analogue circuitry, power sequencing, monitoring, board management, and interfaces including I2C, SPI, and GPIO.
Analyse PCIe and Ethernet links, DDR memory interfaces, clocks, and other timing-critical signals.
Perform feasibility studies, PCB stack-up and materials analysis, controlled-impedance work, routing and layout reviews, and pre-layout and post-layout simulation.
Compare simulations with laboratory measurements, investigate issues, and take increasing ownership of defined circuits, subsystems, analyses, and interface reviews through design release.
Requirements
Recently completed or soon-to-complete degree in Electronic Engineering, Electrical and Electronic Engineering, Computer Engineering, Physics, or a closely related technical discipline.
Strong foundations in analogue and digital electronics, with an interest in hardware design or signal integrity and complete-system and interconnect behaviour.
A logical, first-principles approach to unfamiliar problems and structured debugging, demonstrated through practical engineering work.
Ability to use measurements or technical data to test hypotheses and explain conclusions.
Clear communication, curiosity, willingness to take ownership, and willingness to learn from feedback.
Relevant evidence may come from a final-year project, laboratory work, placement, internship, personal or team project, Formula Student, robotics, engineering society, or other engineering experience.
Nice to have
Interests in schematics, PCBs, component selection, bring-up, validation, testing, or fault finding.
Interests in transmission lines, impedance, reflections, crosstalk, simulation, or electronic measurement.
Previous professional experience with Mentor Expedition, Ansys HFSS, or Keysight ADS is not required.
Culture & Benefits
Permanent role with a two-year graduate programme focused on hands-on learning, design reviews, laboratory work, implementation, validation, and release.
Collaboration with PCB layout, silicon, validation, firmware, mechanical and thermal engineering, manufacturing, and system teams.
Flexible working and thoughtfully designed office spaces with free food and an on-site barista.
Up to 5% matched pension, phantom equity, income protection, and life assurance.
Electric vehicle salary-sacrifice scheme and optional private medical, dental, health cash plan, cycle-to-work, and give-as-you-earn benefits.
Inclusive environment with interview adjustments available on request.
Hiring process
Submit application questions, CV, and cover letter.
Application outcome is expected by early December; successful candidates complete a technical assessment.
Final-stage candidates attend in-person assessments in early spring.
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