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3 дня назад

Senior FPGA Engineer

160 000 - 290 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior FPGA Engineer (Radar/Sensor Systems): Designing and implementing complex FPGA designs for next-generation radar and sensor products with an accent on RTL development, FPGA lifecycle management, and software-system integration. Focus on high-performance signal processing, AXI-based architectures, hardware integration, and validating deployed FPGA capabilities for U.S. and international customers.

Location: El Segundo, California, United States; full-time on-site work in the Hawthorne, California office. U.S. Person status is required to access U.S.-only data systems.

Salary: $160,000–$290,000 base per year, excluding bonuses, equity, and benefits.

Company

hirify.global develops advanced sensing and detection products for defense, commercial air operators, and border protection teams using Coherent Distributed Networks.

What you will do

  • Design and implement complex FPGA systems for next-generation radar and sensor products.
  • Develop RTL designs and support the complete FPGA design lifecycle, including simulation, place and route, timing analysis, and hardware integration.
  • Integrate FPGA designs with complex software systems and modify drivers or applications when needed for validation.
  • Support deployed FPGA capabilities used by U.S. and international customers.
  • Collaborate across R&D and product engineering teams and work with minimal supervision on small teams.

Requirements

  • Bachelor’s or higher degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
  • 5+ years of professional experience performing detailed digital RTL design targeting FPGAs.
  • Extensive experience with the full FPGA design lifecycle: RTL design, behavioral simulation, place and route, timing analysis, and hardware integration.
  • Extensive experience with Verilog, SystemVerilog, ARM AMBA AXI protocols including AXI4, AXI4-Lite, and AXI4-Stream, and AMD (Xilinx) Vivado Design Suite with SoC FPGAs including Zynq, Ultrascale/Ultrascale+, and Versal.
  • Experience with network protocols including TCP, UDP, and IP, and serial protocols including I2C, JTAG, UART, SPI, and CAN.
  • Experience using Bash and Python for scripting and testing.
  • Experience modifying software drivers and applications to validate FPGA designs.
  • Experience with Agile lifecycle processes including Scrum, Continuous Integration, and Test-Driven Development.
  • U.S. Person status and the ability to work full-time on-site in Hawthorne, California.

Nice to have

  • Experience designing high-performance FPGA baseband signal processing and translating algorithms from Simulink, MATLAB, or similar tools into RTL, including FPGA vendor IP implementations.
  • Experience developing C, C++, or Python drivers for FPGA designs and working with FPGA Ethernet IP blocks from 1G to 100G.
  • Experience with Software-Defined Radios, Analog Devices transceivers, and ground or airborne sensors such as radars, EO/IR, or EW systems.
  • Experience with NTP/PTP time synchronization, HLS synthesis, C/C++/SystemC/Chisel, VHDL, and high-speed multilayer digital PCB design.
  • Current or previous DoD security clearance and experience with GPUs or AI engines.
  • Experience with Git, Bitbucket CI, Jenkins, or similar CI/CD flows.
  • Experience with DoD and related system/software architectures and messaging standards such as OMS, SOSA, or Link-16.

Culture & Benefits

  • Medical, dental, and vision benefits fully paid by the company.
  • 401(k) with a 50% company match up to 6% of pay, plus FSA, HSA, and life insurance.
  • Free daily lunch, no-meeting Fridays, unlimited PTO, and a casual dress code.
  • Competitive base salary, pre-IPO stock options, relocation assistance, and planned annual bonuses.
  • Work within a 500-person organization operating across five global offices.

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