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6 дней назад

IP Design PEY Intern (FPGA)

90 000 - 100 000CAD
Формат работы
onsite
Тип работы
fulltime
Грейд
trainee
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
IP Design PEY Intern (FPGA): Developing and verifying configurable FPGA IP cores for external memory and high-speed I/O interfaces with an accent on RTL design, protocol support, and CAD tool integration. Focus on designing for DDR, LPDDR, and MIPI devices, building verification frameworks and simulation models, and debugging hardware during power-on.

Location: Toronto, Ontario, Canada

Salary: $90,000–$100,000 CAD annually

Company

hirify.global is an independent FPGA solutions provider developing programmable technologies for AI, cloud, networking, and edge markets.

What you will do

  • Design FPGA IP architectures based on DDR, LPDDR, and MIPI protocol specifications.
  • Develop RTL and integrate IP with the Quartus Prime CAD tool.
  • Develop verification IP, methodologies, frameworks, bus functional models, and regression tests.
  • Create design examples, simulation models, and technical documentation.
  • Support hardware power-on, debug, product release, rollout, and customer technical support.
  • Collaborate with silicon design and validation, post-silicon validation, application engineering, and customer experience teams.

Requirements

  • Currently pursuing a BS degree in Computer Engineering, Engineering Science, Electrical Engineering, Computer Science, or a related field.
  • At least 3 months of experience in digital logic hardware design or verification using SystemVerilog, Verilog, and/or VHDL.
  • At least 3 months of experience with scripting languages and/or software programming, including Python, TCL, Perl, and/or C/C++.
  • Strong communication, initiative, innovation, teamwork, problem-solving, and attention to detail.
  • Ability to learn and adapt to changing technologies and environments.
  • Accountability, integrity, a winning mindset, collaborative behavior, influencing skills, and willingness to work across geographical locations.
  • Applicants must be eligible for any required Canada export authorizations.

Nice to have

  • FPGA design experience.
  • Experience with RTL simulation, timing closure, and static timing analysis.
  • Experience with DDR, LPDDR, or MIPI hardware interfaces.

Culture & Benefits

  • Full-time student/intern position for a fixed term.
  • Performance-based incentive opportunities in addition to base salary.
  • Canadian work experience is not required.
  • Artificial intelligence is used to screen, assess, or select applicants.

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