Senior AI Systems Architect/Researcher

Location: On-site in Hillsboro, Oregon, United States; additional locations in Folsom and Santa Clara, California.

Annual salary: $195,200–$275,580 USD.

Company

hirify.global's Central Engineering Group Networking Architecture team develops next-generation networking silicon and platform architecture for hyperscale data centers, cloud infrastructure, and AI workloads.

What you will do

• Analyze AI training and serving workloads, identify communication and memory bottlenecks, and translate findings into IP, offload engines, platform features, and architecture requirements.
• Drive hardware-software co-design across compute, DPU/IPU, NIC, SoC fabric, and AI serving runtimes, including vLLM and SGLang.
• Define data movement architecture across xPU-to-xPU, xPU-to-storage, and cross-node paths involving IPU/DPU platforms, NICs, and heterogeneous storage.
• Shape packet processing, RDMA-class transport, and programmable networking IP for hyperscale AI inference and training.
• Investigate KV-cache transfer, disaggregated prefill/decode, model and tensor parallelism, communication collectives, and memory-hierarchy bottlenecks.
• Set multi-generation compute, memory, and interconnect roadmaps and align networking, SoC fabric, firmware/OS/drivers, and performance modeling teams.

Requirements

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 5+ years of relevant experience; or a PhD in one of these fields with 2+ years of relevant experience.
• Experience with modern AI training and/or inference systems, including model architecture internals, hardware algorithm code design, serving runtimes, and memory and data-movement bottlenecks.
• Hands-on experience with inference and training serving stacks such as vLLM and SGLang, including disaggregated prefill/decode, model parallelism, tensor parallelism, and related communication patterns.
• Experience in computer architecture and system-level design focused on networking, interconnect, or memory subsystems.
• Proficiency in C/C++ and/or Python.
• Architectural vision across AI systems, networking, memory, and software; systems thinking across compute, memory, network, and software; and sound decision-making under ambiguity.
• Ability to influence without authority, collaborate across disciplines, translate workload needs into architectural innovation, drive initiatives end-to-end, and stay current with AI systems, inference runtimes, interconnects, memory technologies, and cloud infrastructure.

Nice to have

• Experience analyzing memory hierarchy and system bottlenecks, including caches, memory controllers, bandwidth/latency tradeoffs, and the memory wall.
• Experience with high-performance networking and data-movement technologies such as RDMA/RoCE, InfiniBand, or equivalent transport and interconnect.
• Experience with IPU, DPU, SmartNIC, or accelerator-centric SoCs in cloud and hyperscale environments.
• Familiarity with PCIe, CXL, and memory semantics for high-performance I/O.
• Experience defining architecture from concept through silicon, platform software, or shipped product, including translating workload analysis into architecture requirements and new IP.
• Track record of cross-team technical leadership and influencing architecture and roadmap at a senior level.

Culture & Benefits

• On-site work model with Shift 1 scheduling in the United States.
• Competitive annual compensation, stock bonuses, health benefits, retirement benefits, and vacation.
• Benefits are available for employees and their families through every stage of life.
• Employment with an experienced-hire position at hirify.global.