Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Чётко описанная клиентская роль в области верификации в крупной EDA-компании даёт ценный профильный опыт, но работа проходит в офисе в Южной Корее и включает много поддержки и обучения клиентов.
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Современные технологии
Сильный профильный бренд
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Customer Engagement Engineer II - Xcelium (Hardware Verification/Xcelium): Supporting customer evaluations, verification projects, technical training, and advanced demonstrations for Cadence’s functional logic verification platform with an accent on HDL simulation, RTL design and verification, and customer-facing technical expertise. Focus on applying SystemVerilog, Verilog, VHDL, SystemC, UVM, coverage analysis, and performance profiling to solve complex hardware verification challenges.
Location: Gyeonggi-do (Seoul), Republic of Korea
Company
hirify.global develops technology and tools for electronic design and functional logic verification.
What you will do
Work with R&D to identify and scope opportunities for the hirify.global functional logic verification platform.
Plan, execute, and manage technical evaluations with current and prospective customers and internal colleagues.
Train, ramp up, and accompany customers through verification projects.
Deliver basic and advanced trainings, presentations, and product demonstrations.
Provide expert technical support for customer queries and share project summaries with managers and the team.
Ramp up team members on advanced verification technologies and tools.
Requirements
BS degree in Computer Science or Electrical Engineering and 3–5 years of industry experience.
At least 3 years of hands-on expertise in hardware design and verification techniques.
Hands-on experience with an HDL simulator such as IES, VCS, or Questa; IES is preferred.
RTL design or verification experience using Verilog, SystemVerilog, C/C++, or SystemC.
Hands-on verification experience using SystemVerilog, Verilog, VHDL, or SystemC.
Understanding of standard bus protocols such as AMBA or interface protocols.
Hands-on design experience using SystemVerilog, Verilog, and VHDL.
Knowledge of VIPs and code and functional coverage tools and technologies, with IMC preferred.
Good English communication skills and a strong desire to work in a global environment with customers and business-unit colleagues.
Nice to have
Experience with the UVM methodology or a similar methodology.
Knowledge of Metric Driven Verification using vManager CS.
Hands-on experience optimizing RTL and gate-level simulation performance with standard profiling tools.
Culture & Benefits
Full-time role based in Gyeonggi-do (Seoul), Republic of Korea.
Opportunity to work with R&D, customers, and business-unit colleagues in a global environment.
Focus on technology leadership, innovation, and solving complex verification challenges.
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