Embedded SW/Firmware Design Engineer (FPGA)

Location: Full-time on-site in Hawthorne, California, United States.

Salary: $160,000–$290,000 base salary per year, excluding bonuses, equity, and benefits.

Company

hirify.global develops advanced sensing and detection solutions based on Coherent Distributed Networks for defense, commercial air operators, and border protection teams.

What you will do

• Design and implement complex FPGA systems for next-generation radar and sensor products.
• Support integration of FPGA designs with complex software systems.
• Work across multiple product capabilities and expand expertise across product families.
• Support FPGA capabilities deployed with U.S. and international customers.

Requirements

• Bachelor’s or higher degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
• 5+ years of professional experience performing detailed digital RTL design targeting FPGAs.
• Extensive experience across the FPGA design lifecycle, including RTL design, behavioral simulation, place and route, timing analysis, and hardware integration.
• Extensive experience with Verilog, SystemVerilog, ARM AMBA AXI protocols including AXI4, AXI4-Lite, and AXI4-Stream, and AMD Xilinx Vivado Design Suite with SoC FPGAs including Zynq, Ultrascale/Ultrascale+, and Versal.
• Experience with network protocols including TCP, UDP, and IP, and serial protocols including I2C, JTAG, UART, SPI, and CAN.
• Experience using Bash and Python for scripting and testing.
• Experience modifying software drivers and applications to validate FPGA designs.
• Experience with Agile lifecycle processes, Scrum, Continuous Integration, and Test-Driven Development.
• Ability to work with minimal supervision and collaborate in small teams. U.S. Person status is required to access U.S.-only data systems.

Nice to have

• Experience with high-performance FPGA baseband signal processing and translating algorithms from Simulink, MATLAB, or similar tools into RTL, including FPGA vendor IP implementations.
• Experience developing software drivers in C, C++, or Python for FPGA interfaces.
• Experience with FPGA Ethernet IP blocks, Software-Defined Radios, Analog Device Transceivers, and ground or airborne sensors such as radars, EO/IR, or EW systems.
• Experience with time synchronization technologies including NTP and PTP, HLS synthesis, and C, C++, SystemC, Chisel, or VHDL.
• Experience with high-speed, multi-layer digital PCB design.
• Current or previous DoD security clearance.
• Experience with GPUs, AI engines, Git, Bitbucket CI, Jenkins, or similar CI/CD flows.
• Experience with DoD and related system/software architectures and messaging standards such as OMS, SOSA, and Link-16.

Culture & Benefits

• Medical, dental, and vision benefits fully paid by the company.
• 401(k) with a 50% company match up to 6% of pay, plus FSA, HSA, and life insurance.
• Free daily lunch, no-meeting Fridays, unlimited PTO, and a casual dress code.
• Competitive base salary, pre-IPO stock options, relocation assistance, and planned annual bonuses.
• Approximately 500 employees across five global offices.