Senior OPC R&D Engineer (Semiconductor)

Location: Hybrid role aligned to San Jose, California or Rancho Cordova, California; primarily office-based, with some international travel expected. Open to relocation.

Salary: USD 159,360–255,000 yearly, plus eligibility for RSU, RCU, and cash bonus programs.

Company

hirify.global is a multibillion-dollar memory technology company developing NAND products and data storage solutions, with operations in the United States, Asia, Europe, and the Americas.

What you will do

• Develop, implement, and optimize OPC models and recipes for critical memory patterning layers.
• Apply DFM, RET, and SMO techniques, including test plate design and design rule evaluations.
• Validate OPC tapeout readiness, conduct quality reviews, and resolve patterning hotspot issues with lithography and process integration teams.
• Evaluate OPC performance using validation and simulation tools, wafer data, and mask quality and process-window metrics.
• Create documentation and training for OPC tools and methodologies and provide technical support to internal users.
• Collaborate with design rule, lithography, process integration, tapeout, mask engineering, and manufacturing teams.

Requirements

• MS or PhD in a related science or engineering discipline, such as Physics, Materials Science, Electrical Engineering, or Chemical Engineering.
• At least 5 years of proven technical development experience in semiconductor patterning.
• Strong understanding of optical proximity effects, RET including SMO, DFM methodologies, semiconductor patterning technologies, and patterning concerns.
• Proficiency with industry-standard OPC and SMO software, including Mentor, Synopsys, or ASML Brion tools.
• Proficiency in scripting languages such as Python, TCL, or Perl; experience with C++ may also be required.
• Ability to analyze large datasets, perform statistical analysis, and interpret simulation results.
• Ability to solve complex technical problems related to RET, OPC, tapeout, design rules, and semiconductor patterning processes.
• Strong technical communication and collaboration skills across design, technical development, and manufacturing teams.

Nice to have

• 7 or more years of experience in OPC, RET, or related areas delivering high-quality patterning solutions.
• Strong understanding of semiconductor manufacturing technologies and the overall chip fabrication process, especially NAND flash manufacturing.

Culture & Benefits

• Inclusive, diverse, equitable, collaborative, team-oriented, and results-driven work environment.
• Medical, dental, vision, supplemental life, AD&D, short-term disability, and long-term disability insurance.
• Healthcare and dependent care flexible spending accounts.
• Company match on eligible 401(k) plan contributions.
• Eligibility for restricted stock unit, restricted cash unit, and cash bonus programs.