8 дней назад
FPGA Development Tools Engineer
Вакансия из Hirify Global, списка международных tech-компанийДля мэтча и отклика нужен Plus
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
FPGA Development Tools Engineer (FPGA/Quartus Prime): Developing and automating validation tests, regression infrastructure, and C++ device models for FPGA device and simulation models with an accent on end-to-end Quartus Prime flows, coverage, and release quality. Focus on debugging synthesis, fitter, RTL, constraints, and model failures, integrating validation into CI pipelines, and expanding coverage across device families and architectural variants.
Location: Penang 15, Penang, Malaysia; onsite role
Company
develops FPGA device and simulation technologies supported by the Quartus Prime development environment.
What you will do
- Develop comprehensive test plans and execute targeted and regression tests for FPGA device and simulation models across multiple device families.
- Build and run end-to-end Quartus Prime projects covering synthesis, fitting, and simulation signoff.
- Maintain golden reference results, analyze QoR and performance deltas, and triage warnings, errors, and regressions.
- Create automation and modeling tools with C++, Tcl, Python, and Bash for test generation, execution, log mining, and reporting.
- Develop C++ device model libraries for FPGA architecture blocks such as DSP and memory.
- Integrate validation into Jenkins or GitLab CI pipelines and collaborate with modeling, device, and software teams to resolve root causes.
Requirements
- 4–5 years of relevant engineering experience and a BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Strong knowledge of digital design principles, including combinational and sequential logic, clocking, resets, and pipelining.
- Experience with FPGA or ASIC flows, including RTL with Verilog, SystemVerilog, or VHDL, synthesis, static timing analysis, and SDC constraints.
- Proficiency in Tcl or Python and a working foundation in C++ for hardware or device model development and debugging.
- Familiarity with Linux development environments, build workflows, tool logs, and timing reports.
- Strong problem-solving and technical documentation skills.
Nice to have
- Experience maintaining C++ libraries for hardware, architectural, or device modeling.
- Experience with Quartus Prime, TimeQuest, fitter concepts, Git, Jenkins, or GitLab CI.
- Knowledge of speed grades, PVT corners, I/O standards, clocking networks, and timing signoff concepts.
- Coursework or project experience with FPGA boards, EDA tools, or regression test environments.
Culture & Benefits
- Regular full-time employment.
- Shift 1 schedule aligned with Malaysia.
- Focus on quality, continuous improvement, scalability, and repeatable validation processes.
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