Senior Design Verification Engineer (Space)

Location: Tempe, Arizona, United States. This is a site-based role requiring work from a hirify.global office or work location at least 3 days, or 60%, per week. Up to 10% travel may be required.

Salary: $132,500–$209,500 annually. For specific work locations in San Jose, the San Francisco Bay Area, and the New York City metropolitan area: $164,500–$246,500 annually.

Company

hirify.global develops communications technology serving consumers, businesses, governments, and militaries worldwide.

What you will do

• Plan and execute full-cycle RTL verification for FPGA and ASIC designs, including test plans.
• Develop SystemVerilog/UVM testbenches with drivers, monitors, scoreboards, sequences, and model predictors.
• Debug failing tests and collaborate with RTL developers on VHDL and Verilog source code.
• Collect and analyze code and functional coverage metrics and run verification regressions.
• Manage compute resources, evaluate verification tools, and support license management.
• Track schedules and tasks in Agile Jira workflows and drive technical issues to resolution.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of design verification experience, including UVM testbench development.
• Foundational knowledge of digital logic and timing considerations.
• Experience with Questa, Xcelium, VCS, and industry-standard simulation tools.
• Strong communication skills, attention to detail, process adherence, code reviews, and feedback acceptance.
• US citizenship is required.

Nice to have

• Object-oriented programming and reusable horizontal and vertical testbench design experience.
• Familiarity with CI/CD practices and AI agents such as Claude Code and Copilot.
• Experience working independently with geographically distributed teams.
• Strong troubleshooting, initiative, and ownership skills.

Culture & Benefits

• Work with systems engineers, design engineers, and design verification engineers on communications technology.
• Use current verification methodologies, including UVM and emerging DV AI agentic tools.
• Participate in a collaborative environment focused on quality and time to market.
• Additional cash or stock incentives and medical, financial, and other benefits may be available depending on the position.