SerDes Characterization & Post-Silicon Validation Engineer (Aerospace)

Location: Los Angeles, California, United States; onsite role. The hired candidate must be a U.S. person under ITAR or otherwise eligible for a federally issued export-control license.

Salary: $170,000–$250,000 annually, plus company equity.

Company

hirify.global develops and mass-produces high-power satellite platforms for missions ranging from low Earth orbit to deep space.

What you will do

• Lead post-silicon bring-up and characterization of high-speed NRZ and PAM4 SerDes, including 112G-class interfaces.
• Develop electrical characterization plans covering lanes, data rates, voltage, temperature, channels, and operating conditions.
• Measure eye quality, jitter, amplitude, linearity, equalization, receiver sensitivity, BER, bathtub curves, CDR performance, and link margin.
• Debug link issues across SerDes IP, clocks, power, packages, PCBs, firmware, digital logic, and systems.
• Correlate silicon measurements with SerDes models, simulations, and signal-integrity analysis.
• Build automated test, regression, measurement, reporting, and high-speed validation infrastructure.

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of experience in high-speed SerDes characterization, post-silicon validation, signal integrity, or a related area.
• Strong knowledge of NRZ/PAM4 signaling, equalization, CDR, jitter, BER, channel loss, and link budgets.
• Hands-on experience with high-bandwidth oscilloscopes, BERTs, pattern generators, VNAs, TDR/TDT, and high-speed electrical measurement equipment.
• Experience with eye diagrams, jitter decomposition, bathtub curves, BER and stressed-eye testing, receiver sensitivity, package/PCB channels, crosstalk, reflections, and channel de-embedding.
• Experience developing automated characterization environments with Python or similar scripting languages and instrument-control interfaces.

Nice to have

• Experience with 112G+ PAM4 SerDes, Ethernet, PCIe, JESD204, Interlaken, or chip-to-chip interfaces.
• Experience with compliance testing, SerDes models, simulation-to-measurement correlation, and third-party SerDes IP integration.
• Experience with advanced packages, high-loss PCB channels, high-speed clocking, PLLs, reference-clock jitter, and power-supply noise effects.
• Experience with automated PVT characterization and large-scale measurement data analysis.

Culture & Benefits

• Work in a high-growth, Series D-funded aerospace company developing large satellite platforms.
• Comprehensive benefits including paid time off, medical, dental and vision coverage, life insurance, and paid parental leave.
• Equity in the company.
• Non-traditional career paths and varied professional experience are encouraged.