System Level Test (SLT) Content Development and Debug Engineer (FPGA)

Location: Penang 15, Penang, Malaysia

Company

hirify.global develops programmable hardware, software, and development tools, including FPGAs, CPLDs, IP, SmartNICs, IPUs, and system-on-module products.

What you will do

• Define test plans, test methods, execution procedures, data analysis, and automated verification flows for FPGA, transceiver, and multi-chip package products.
• Develop build automation, regression scripts, and test content for bench and automatic test equipment.
• Debug production rejects and customer-reported failures to identify root causes and close test gaps.
• Work with hardware, software, silicon validation, manufacturing, integration, and customer support teams to evaluate system performance and device functionality.
• Define product health indicators and reduce defects per million through improved test coverage.
• Create platform validation documentation, including risk assessments, test plans, user acceptance tests, and reports.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Experience defining and executing system-level, platform, silicon, or product validation plans and test methods.
• Experience developing automated tests, regression or verification scripts, analyzing data, and debugging failures to root cause.
• Experience collaborating with hardware architecture and design, silicon validation, software, integration, process engineering, and manufacturing teams.
• Experience validating and characterizing system performance, timing, power, thermal behavior, or hardware-software interaction using bench or automatic test equipment.

Nice to have

• Experience developing FPGA or multi-chip package test content and vectors for IP subsystems such as core, configuration, transceiver, HPS, EMIF, LVDS, and MIPI.
• Experience maintaining test frameworks, regression infrastructure, or enterprise-service integrations.
• Knowledge of Verilog, VHDL, Quartus Prime RTL generation, timing closure, TCL, or Python.
• Experience with production test equipment and manufacturing test methodologies.

Culture & Benefits

• Regular full-time employment.
• Shift 1 schedule in Malaysia.
• Cross-functional work across engineering, manufacturing, validation, and customer support.