4 дня назад
Member of Technical Staff, Hardware, Compiler Engineer (AI)
200 000 - 420 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Member of Technical Staff, Hardware, Compiler Engineer (AI) (MLIR/LLVM/PyTorch/custom silicon): Building a compiler stack that lowers PyTorch graphs into optimized custom ISA assembly for high-performance AI hardware with an accent on graph optimization, backend development, and hardware-software co-design. Focus on designing tiling and fusion transformations, integrating high-performance kernels, closing compilation gaps through profiling, and evolving custom ISA definitions with silicon architects.
Location: Based in Austin, Texas or Palo Alto, California, United States
Annual salary: $200,000–$420,000 USD
Company
develops personal AI systems spanning local-inference hardware, custom training infrastructure, user interfaces, and deep learning research.
What you will do
- Design compiler passes that lower PyTorch models to custom hardware using MLIR dialects and LLVM frameworks.
- Develop the backend toolchain for custom silicon, including instruction scheduling, register allocation, and hardware-specific code generation.
- Implement tiling and fusion strategies to improve bandwidth utilization and reduce on-chip memory movement.
- Integrate high-performance Triton/CUDA-like kernels into the automated compiler flow.
- Profile compiler performance, identify compilation gaps, and implement targeted optimizations.
- Collaborate with AI researchers, modelers, performance engineers, RTL teams, and silicon architects on hardware-software co-design and custom ISA changes.
Requirements
- Bachelor’s degree in Electrical Engineering or Computer Engineering and 5+ years of practical industry experience with advanced process nodes of 7nm or below.
- Deep hands-on experience with MLIR or XLA for deep learning workloads.
- Expert understanding of PyTorch internals and integration with external backends.
- Proficiency in modern C/C++ for scalable, high-performance compiler infrastructure.
- Advanced knowledge of computer architecture and the programming model of at least one chip type, such as SoCs, CPUs, GPUs, or AI accelerators.
- Collaborative approach to compiler, hardware, and software co-design.
Nice to have
- Experience with post-silicon firmware and model update patches.
- Experience defining custom dialects, lowering passes, and graph rewrites in an LLVM-based ecosystem.
- Knowledge of static and runtime environments, including JITs and ABIs.
Culture & Benefits
- Visa sponsorship is available, subject to candidate and role fit.
- Relocation support is provided as needed.
- Health, dental, and vision benefits.
- Unlimited paid time off.
- Collaboration across AI research, performance engineering, hardware, RTL, and architecture teams.
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