обновлено 1 месяц назад
FPGA Compiler (Placer) Engineer
129 100 - 187 000CAD
Вакансия из Hirify Global, списка международных tech-компанийДля мэтча и отклика нужен Plus
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
FPGA Compiler (Placer) Engineer (FPGA/EDA): Design and optimize FPGA placement algorithms within compiler toolchains, improving timing, congestion, resource utilization, runtime, and quality of results with an accent on timing-driven placement and large-scale optimization. Focus on developing scalable heuristics, analyzing congestion and timing bottlenecks, integrating placement capabilities, and solving complex physical-design challenges for advanced FPGA architectures.
Location: Toronto, Ontario, Canada
Salary: CAD 129,100–187,000 per year, plus performance-based incentive opportunities
Company
is an independent FPGA solutions provider developing programmable technologies for AI, cloud computing, networking, and edge applications.
What you will do
- Design, implement, and enhance FPGA placement algorithms for timing, congestion, and resource-utilization optimization.
- Contribute to the end-to-end FPGA compilation flow alongside routing, synthesis, and timing teams.
- Improve runtime performance, scalability, and quality of results for large customer designs.
- Develop timing-aware and congestion-driven placement strategies for performance-critical designs.
- Analyze placement quality, congestion hotspots, and timing bottlenecks to improve convergence and design closure.
- Integrate placement capabilities into the compiler infrastructure and validate them across diverse workloads.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- At least 6 years of experience in FPGA/ASIC CAD, EDA tools, or related fields.
- Strong knowledge of algorithms and data structures, including optimization, graph theory, and heuristics.
- Experience with placement algorithms, physical design flows, analytical placement, simulated annealing, partitioning, or clustering.
- Professional experience with C/C++ and software engineering best practices.
- Applicants must be eligible for any required Canada export authorizations. Canadian work experience is not required.
Nice to have
- Experience with FPGA toolchains such as Quartus or Vivado.
- Knowledge of FPGA architectures and interconnect fabrics.
- Familiarity with routing and timing-closure techniques.
- Experience with parallel or distributed algorithms for EDA tools.
- Scripting experience with Python or Tcl for tooling and automation.
Culture & Benefits
- Work on core compiler technology that directly impacts FPGA performance and usability.
- Solve challenging algorithmic problems at scale.
- Collaborate with teams across architecture, silicon, and software.
- Receive performance-based incentive opportunities tied to individual and company results.
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