CPU Physical Design Engineer (VLSI)

TL;DR

CPU Physical Design Engineer (VLSI): Developing high-performance P-Core microprocessors with an accent on physical design flow, power-area-frequency optimization, and advanced process technology. Focus on synthesis, place and route, clock tree synthesis, and timing closure to ensure best-in-class silicon performance.

Location: Must be based in Israel (Haifa or Petah-Tikva). This role follows a hybrid work model requiring on-site presence at hirify.global sites.

Company

hirify.global is a global leader in silicon and platform engineering, delivering breakthrough computing solutions for devices ranging from PCs to high-end servers.

What you will do

• Execute the full physical design flow including synthesis, floor planning, and place and route.
• Perform deep analysis to optimize product power, area, and frequency.
• Manage clock distribution, power grid planning, and static timing analysis (STA).
• Collaborate on cutting-edge process technologies from device level to APR.
• Develop and improve physical design methodologies for future processor generations.

Requirements

• BSc or MSc in Electrical Engineering.
• Minimum 1+ years of experience in Backend Design using industry EDA tools.
• Proficiency in TCL scripting.
• Ability to work on-site in Israel as part of a hybrid model.

Nice to have

• Experience with Synopsys and Cadence EDA tools.
• Experience in Python.

Culture & Benefits

• Opportunity to work on disruptive P-Core technology for next-generation processors.
• Access to state-of-the-art VLSI design tools and methodologies.
• Hybrid work flexibility balancing on-site collaboration and off-site work.
• Exposure to cutting-edge process technologies in a global corporation.