E-core CPU Layout Design Engineer (Silicon)

TL;DR

E-core CPU Layout Design Engineer (Silicon): Driving the physical implementation of memory compilers and RF custom IP blocks for high-performance hirify.global Atom microprocessors with an accent on transistor-level planning, assembly, and routing. Focus on solving complex layout challenges, performing reliability verification, and establishing design methodologies in a dynamic silicon engineering environment.

Location: Must be based in Penang, Malaysia (Hybrid work model)

Company

hirify.global is a global leader in silicon and platform engineering, delivering breakthrough computing solutions and next-generation technology products.

What you will do

• Drive physical implementation of memory compilers and RF custom IP blocks.
• Perform transistor, device, and cell-level planning, layout, assembly, and routing.
• Utilize CAD tools for layout editing, verification, and Design for Manufacturing (DFM).
• Conduct engineering analysis for IR drop, electromigration, and self-heat reliability.
• Collaborate with Design Automation teams to define and refine layout methodologies.
• Independently plan complex layout assignments and manage project schedules.

Requirements

• Bachelor's or Master's degree in Electronic/Microelectronic Engineering, Computer Engineering, or related discipline.
• 10+ years of experience in layout design.
• Proficiency in programming with UNIX shell scripts, Tcl, and Perl.
• Strong analytical, problem-solving, and interpersonal skills.
• Excellent verbal and written communication skills.

Culture & Benefits

• Hybrid work model allowing flexibility between on-site and off-site work.
• Opportunity to work on future-generation high-performance microprocessor architectures.
• Collaborative environment within the Silicon and Platform Engineering Group.
• Commitment to ethical hiring practices and Responsible Business Alliance (RBA) compliance.