Principal Analog Circuit Design Engineer (SerDes)

TL;DR

Principal Analog Circuit Design Engineer (SerDes): Designing and building high-speed analog and mixed-signal IPs for advanced process nodes with an accent on SerDes architecture, signal integrity, and performance optimization. Focus on driving technical strategy, mentoring technical leaders, and ensuring robust execution for next-generation communication standards like PCIe and Ethernet.

Location: Must be based in the greater metropolitan area of Toronto, Ontario. This role will transition to a hybrid model (4 days/week on-site) once the local office is operational.

Salary: CAD 214,452–302,753

Company

hirify.global is a global leader in semiconductor technology, building scalable engineering solutions across product enablement, custom ASIC, and foundry services.

What you will do

• Design and build analog circuits in advanced process nodes for mixed-signal IPs.
• Create test plans and evaluate results to optimize for power, performance, area, and yield.
• Collaborate cross-functionally to track design progress and resolve performance issues.
• Influence technical direction as a domain expert across the industry.
• Develop and mentor technical leaders to foster a strong engineering community.
• Formulate technical strategy to deliver leadership solutions for product and foundry businesses.

Requirements

• Master's degree in Electrical or Electronics Engineering.
• Must be based in the greater metropolitan area of Toronto, Ontario.
• 8+ years of experience in analog/mixed-signal circuit design for high-speed SerDes.
• Proven expertise in PLL, CDR, CTLE, DFE, ADC, or Transmitter design.
• Solid knowledge of high-speed standards like PCIe (Gen5/Gen6) and Ethernet (100G/400G/800G).
• Hands-on experience with FinFET CMOS process technologies (7nm or below).
• Proficiency in Cadence Virtuoso/ADE and HSPICE.

Nice to have

• Ph.D. in Electrical or Electronics Engineering.
• 10+ years of experience in high-speed SerDes (56G/112G/224G).
• Experience with behavioral modeling (Verilog-A), MATLAB, and Python/Tcl/Perl scripting.
• Familiarity with PCIe 6.0+ and 800G/1.6T Ethernet standards.

Culture & Benefits

• Commitment to a culture of accessibility and inclusive hiring.
• Opportunity to influence industry-wide technical standards.
• Collaborative environment focused on end-to-end engineering solutions.
• Support for professional growth through mentorship and leadership opportunities.