Hardware & Silicon Validation Senior Staff Engineer

TL;DR

Hardware & Silicon Validation Senior Staff Engineer: Ensuring the quality, reliability, and performance of next-generation data center ASIC and SoC products with an accent on functional hardware validation, electrical characterization, and high-speed SERDES validation. Focus on validating complex, high-performance silicon and platforms across a wide range of critical technologies and interfaces.

Location: Santa Clara, CA

Salary: 127,630 - 191,200 USD per annum

Company

hirify.global’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.

What you will do

• Lead electrical characterization, compliance, and debug for SerDes IP targeting Ethernet IEEE 802.3ck/dj and PCIe Gen5/Gen6 standards at 112G/224G data rates.
• Develop and implement automated validation methodologies, regression frameworks, and compliance test plans for SerDes interfaces across multiple product lines.
• Drive signal integrity analysis and optimization for high-speed channels, including correlation between pre-silicon modeling, simulation, and lab measurements.
• Provide technical leadership and applications engineering support to strategic customers, including on-site debug and performance optimization.
• Mentor and develop staff-level and junior engineers in high-speed signal integrity measurement techniques, debug methodologies, and test automation best practices.
• Contribute to high-speed board design reviews, extraction, and characterization; partner with internal tools teams to build robust test infrastructure.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 3–15 years of relevant industry experience; or Master’s degree and/or PhD in Computer Science, Electrical Engineering, or a related discipline with 2–10 years of professional experience.
• 5–7+ years of direct experience in SerDes characterization, design, or signal integrity engineering.
• Deep expertise in Ethernet IEEE 802.3ck/dj electrical compliance and validation, and/or PCIe Gen5/Gen6 specifications.
• Strong knowledge of signal integrity principles, channel modeling, S-parameter analysis, equalization architectures (CTLE, DFE, FFE), and board-level design for high-speed interfaces.
• In-depth working knowledge of test equipment used for SerDes characterization: real-time and sampling oscilloscopes, BERTs, vector network analyzers, pattern generators, and protocol analyzers.
• Strong proficiency in Python scripting for test automation, data analysis, and regression infrastructure development.

Nice to have

• Experience with high-speed PCB design, signal integrity simulation tools (HFSS, ADS, Sigrity, or equivalent), and channel extraction methodologies is preferred
• Active participation or familiarity with IEEE 802.3 or PCI-SIG standards committees is preferred.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental health resources to prioritize emotional well-being.
• Recognition and service awards to celebrate contributions and milestones.