Senior Staff Digital Design Engineer (ASIC)

TL;DR

Senior Staff Digital Design Engineer (ASIC): Designing and implementing digital ASICs for high-performance connectivity silicon that underpins AI scale data centers with an accent on advanced digital pipelines, high speed datapaths, and DSP driven processing engines. Focus on translating high-level requirements into detailed micro-architecture specifications and driving the full ASIC front-end design flow.

Location: Irvine, CA; Santa Clara, CA; San Jose, CA

Salary: 135,900 - 201,130 USD per annum

Company

hirify.global’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.

What you will do

• Collaborate with systems and architecture teams to define SoC‑level specifications.
• Translate high‑level product and protocol requirements into detailed micro‑architecture specifications.
• Own RTL development for assigned blocks, delivering high‑quality, synthesizable SystemVerilog RTL.
• Implement and drive the full ASIC front‑end design flow.
• Partner with STA and PNR teams to support timing closure, floorplanning, and congestion analysis.
• Drive post‑silicon bring‑up and debug, collaborating with lab and systems teams to validate functionality.

Requirements

• Extensive experience in digital ASIC design, including micro‑architecture development and RTL implementation.
• 10+ years of industry experience working on large‑scale ASICs for networking, data‑center connectivity, or high‑bandwidth compute architectures.
• Strong background in high‑performance DSP and high‑speed datapath design.
• Familiarity with Ethernet protocols and networking standards.
• Proficiency with front‑end design flows, including lint, CDC/RDC, synthesis, STA, and power/performance optimization.
• BS/MS in Electrical Engineering, Computer Engineering, or related field.

Nice to have

• Advanced high‑speed DSP algorithm implementation.
• Experience with FEC architectures such as LDPC, RS, BCH, or other high‑speed coding/decoding schemes used in networking and optical interconnects.
• Previous PHY design experience, including PMA‑level DSP pipelines, equalization blocks, clock recovery, and SerDes‑adjacent logic.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental health resources to prioritize emotional well-being.
• Recognition and service awards to celebrate contributions and milestones.