Staff Design Verification Engineer (ASIC/UVM)

TL;DR

Staff Design Verification Engineer (ASIC/UVM): Designing, verifying, and evaluating digital circuits in high-speed data communication ICs with an accent on SerDes IP solutions, UVM environment improvement, and design methodology. Focus on collaborating with cross-functional teams and providing pre/post silicon support for competitive IP solutions.

Location: Toronto, Canada (onsite)

Salary: CAD 98,100–130,800 per annum

Company

hirify.global provides essential semiconductor solutions for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Perform design verification for various types of SerDes IPs (10Gbps to 224Gbps).
• Utilize and enhance the UVM DV environment.
• Improve design methodology and flow.
• Collaborate with Analog, DSP, Digital Design, FW, and AE teams to deliver competitive SerDes IP solutions.
• Provide pre and post silicon support to product teams.

Requirements

• Bachelor’s degree in Computer Engineering or Electrical Engineering with 4+ years of experience, or Master’s/PhD with 2+ years.
• Proficiency in fundamental concepts of digital logic design.
• Understanding of ASIC verification flows and methodologies.
• Expertise in Verilog, SystemVerilog, and UVM.
• Proficiency in UNIX Shell scripting (Csh, Bash).
• Good communication and leadership skills to work with a global team.

Nice to have

• Experience with VIPs and Formal verification.
• PCIe, UCIe protocol knowledge.
• Experience with low power design.
• MATLAB and C/C++ based system simulation and evaluation.
• DSP function hardware implementation knowledge.
• Strong Perl and Python scripting skills.

Culture & Benefits

• Competitive compensation and great benefits.
• Workstyle within an environment of shared collaboration, transparency, and inclusivity.
• Opportunity for growth and development with tools and resources.
• All qualified applicants receive consideration for employment without regard to protected characteristics.
• AI tools are not permitted during interviews to support fair and authentic hiring practices.