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1 день назад

Design Engineer (AI SoC)

153 910 - 217 280CAD
Формат работы
remote (только Canada)
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

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TL;DR

Design Engineer (AI SoC): Develops logic design, RTL coding, and simulation for AI SoC products with an accent on architectural trade-offs, IP integration, and timing closure. Focus on implementing RTL in Verilog/SystemVerilog, collaborating with verification teams, and supporting silicon bring-up and post-silicon validation.

Location: Remote (Canada only)

Salary: CAD 153,910.00–217,280.00

Company

hirify.global's AI SoC organization develops cutting-edge products for a wide range of AI applications, from edge devices to data center accelerators.

What you will do

  • Contribute to architectural trade-off evaluations considering features, performance, and system constraints.
  • Implement RTL in Verilog/SystemVerilog and integrate IP blocks for synthesis and timing-clean design.
  • Collaborate with verification teams to achieve full coverage and robust validation.
  • Develop timing constraints and assist physical design teams with synthesis, timing closure, and formal equivalence checks.
  • Support silicon bring-up and post-silicon validation activities, including debug and performance analysis.
  • Collaborate with senior engineers to adopt best practices and improve design methodologies.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
  • 5+ years of experience in RTL design and implementation for ASIC/SoC development.
  • Proficiency in Verilog/SystemVerilog for RTL coding and design.
  • Experience with synthesis tools and timing closure methodologies.
  • Strong technical and communication skills.

Nice to have

  • Understanding of clock domain crossings, power optimization, and timing closure.
  • Exposure to SoC system integration and CPU subsystem design.
  • Familiarity with standard bus protocols (AXI, AHB, etc.) and embedded processor architectures.
  • Basic scripting skills (Python, TCL, etc.) for automation.
  • Experience with static timing analysis (STA) and formal verification tools.

Culture & Benefits

  • Fast-paced environment with abundant learning opportunities.
  • Culture of accessibility with accommodations for disabilities.
  • Committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.
  • No fees charged during the hiring process.

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