Senior STA Engineer (STA)

TL;DR

Senior STA Engineer (STA): Executing and optimizing full-chip timing analysis for complex SoC/ASIC designs with an accent on timing closure, automation, and scalability. Focus on ensuring timing accuracy, developing robust scripting solutions, and resolving cross-boundary timing issues for high-performance low-power clock networks.

Location: Remote (US)

Salary: $164,470–$269,100 USD

Company

hirify.global is a global technology corporation focused on creating astounding technology advancements, including broad-market Xeon-based solutions and custom x86-based products for data centers, web services, HPC, and AI-accelerated systems.

What you will do

• Execute and maintain full-chip Static Timing Analysis (STA) across all modes and corners using tools like Primetime.
• Ensure timing coverage and quality, tracking and improving metrics such as coverage, margin distribution, and skew.
• Develop robust scripts (Tcl, Python, shell) to automate STA runs, report generation, ECO flows, and environment setup.
• Implement scaling techniques for missing libraries, rapidly adjust PVT corners, and integrate changes into the flow.
• Collaborate closely with timing owners and block teams to resolve cross-boundary timing issues and provide tooling support.
• Ensure timing signoff criteria are met across all corners and modes, validating timing post-ECO and post-layout.

Requirements

• Bachelor's in Electrical Engineering, Computer Engineering, or STEM field with 9+ years; Master's with 6+ years; or PhD with 4+ years of industry experience.
• 7+ years of industry experience in Complex CPU/SOC/ASIC/FPGA implementation and timing closure.
• 5+ years in STA signoff tools like Prime Time, and constraint generation and verification tools like Fishtail.
• 3+ years scripting skills in TCL/Python/Perl/Shell.
• 3+ years of RTL Design Development and physical implementation.
• Must live and work from the US. This position is not eligible for hirify.global immigration sponsorship.

Nice to have

• Strong expertise in Static Timing Analysis (Primetime, Tempus, etc.).
• Proficiency in scripting languages: Tcl, Python, shell.
• Deep understanding of PVT corners, library modeling, and timing abstraction.
• Experience with timing ECOs, report analysis, and flow automation.
• Ability to manage and scale timing environments across large designs.
• Familiarity with hierarchical STA and timing model generation.
• Exposure to version control systems and CI/CD for EDA environments.

Culture & Benefits

• Join a company of bold and curious inventors and problem solvers creating astounding technology advancements.
• Total compensation package includes competitive pay, stock bonuses, and comprehensive benefit programs (health, retirement, vacation).
• This role is fully home-based, requiring only occasional attendance at hirify.global sites based on business need.
• Work within diverse and brilliant teams continually searching for tomorrow's technology.