Foundry Interface Engineer (ASIC)

TL;DR

Foundry Interface Engineer (ASIC): Engaging with foundry partners and internal teams to continuously improve ASIC design, focusing on process fine-tuning, device parameter changes, and analyzing production wafer data to meet technology and product goals. Focus on working with standard cell level circuit designers to analyze results and making requests to the foundry for process fine tuning.

Location: Remote (US only)

Salary: $168,300–$297,000 USD (based on US location zone)

Company

hirify.global, Inc. is a technology company building products like Bitkey (bitcoin wallet) and Proto (bitcoin mining services) to increase access to the global economy.

What you will do

• Engage with Foundry partners and third-party vendors to manage foundry PDK/DK and design library collaterals.
• Guide internal IP/design teams on appropriate usage of technology attributes/offerings based on product requirements.
• Collaborate with various internal teams (infrastructure, customization, test-chip, methodology, packaging, product test engineering) for seamless product bring-up and productization.
• Review and assess Foundry silicon data against SPICE/design goals, compile SPICE to Silicon gap analysis, and drive foundry partners on CIPs.
• Work with foundry to identify potential device parameter changes to enable efficient low-voltage operation.
• Work closely with circuit designers to determine device improvements that could enhance circuit performance and energy efficiency.
• Contribute to binning strategy to maximize parametric yield.

Requirements

• 10+ years of post-education experience in FAB/Fabless environments, technology definition and bring-up, device/process architecture, and NPI.
• Experience with foundry design kit, SPICE, DR/DRC evaluation, and SPICE to Si assessment.
• Experience with advanced node device physics (e.g., FinFET/GAA), backside power, and product design phases.
• Experience with product KPIs, DTCO, and parametric, DLY/PLY analysis/gap closure.
• Understanding of low power design techniques (e.g., Vmin reduction, power gating, multi-voltage design, chip power, clock network and optimization).
• Understanding of layout effects and their impact on circuit design.
• Excellent statistical, data analysis, and communication skills.

Nice to have

• Master's degree or PhD in Electrical Engineering, Physics, or a related Engineering field with emphasis on semiconductor materials/devices and device physics.
• Production test development experience.
• Familiarity with advanced FinFET technology nodes (3nm and 2nm).
• Familiarity with PDK and device models.
• Previous work experience at semiconductor foundries.
• Familiarity with standard cell design and layout.

Culture & Benefits

• Remote work opportunities are available.
• Comprehensive benefits including medical insurance, flexible time off, and retirement savings plans.
• Modern family planning support.
• Commitment to an inclusive interview experience, including providing reasonable accommodations to disabled applicants.
• hirify.global is an equal opportunity employer.

Hiring process

• Automated AI tools may be used to evaluate job applications for efficiency and consistency.
• AI tools comply with local regulations, including bias audits, and personal data is handled in accordance with privacy laws.