TL;DR
Staff / Sr Staff RTL Design Engineer (AI): Contributing to next generation connectivity networking products with an accent on microarchitecture/RTL coding of the SOC/subsystems. Focus on debugging and fixing issues reported by verification team and ensure successful tapeout.
Location: Toronto, Remote - QC
Company
hirify.global enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world.
What you will do
- Micro architect and RTL Design of SoC SubSystem/IP blocks.
- Develop UPF and run CLP checks.
- Responsible for RTL quality checks - Lint/CDC/LEC.
- Create appropriate documentation for hardware blocks.
- Responsible for analyse / debug / fixing issues reported by verification team.
- Work with SOC Architect/Leads to integrate the design, review/sign-off verification plan, DFT and PD implementation.
Requirements
- Strong background with multi-year and multi-project experience in RTL SoC Design (Verilog/VHDL), and ASIC/FPGA debug methodologies.
- Experience in SerDes PHY, DSP, and Analog mixed signal is desirable.
- Knowledge in Ethernet and PCIe standards is desirable.
- Proficient in reviewing high-level test plans and coverage metrics.
- Expertise in Design Compiler Synthesis and formal verification using LEC.
- Comprehensive understanding of timing closure and experience in post-silicon bring-up and debugging.
Nice to have
- Ability to develop architecture and micro-architecture based on specifications.
- Knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc.
- Experience with memory controller designs and microprocessors is an advantage.
- Knowledge of chip IO design and packaging is beneficial.
Culture & Benefits
- Flexible work environment to support and help employees thrive in personal and professional capacities.
- Comprehensive health plans and Wellness Spending Account (WSA).
- Employee Assistance Program (EAP).
- Flexible time off options to support your well-being, including paid vacation, holidays, and parental leave.
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