Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Чёткая роль senior-уровня в разработке передового AI-оборудования с заметной ответственностью за инфраструктуру эмуляции; ограничения экспортного контроля могут сузить круг подходящих специалистов.
Ограничения по экспорту
AI-железо
Понятная зона ответственности
Современный стек
Мэтч & Сопровод
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Senior/Staff Emulation Engineer (AI): Building reusable emulation infrastructure, HW/SW co-emulation flows, and debug tooling for advanced connectivity SoCs with an accent on commercial emulation platforms, transactors, system-level validation, and LLM-based engineering tools. Focus on defining emulation strategies, integrating PCIe, HBM4, Ethernet, AXI/AMBA, JTAG, and SPI models, optimizing performance and resource utilization, and automating regression triage.
Location: Israel; hybrid
Salary: $160,000–$275,000 for early career, $175,000–$400,000 for mid career, or $250,000–$600,000 for senior career, plus equity.
Company
hirify.global develops vertically integrated hardware and software solutions, from silicon to systems, for training and running large machine-learning workloads for AGI.
What you will do
Define and execute emulation strategies and test plans for complex connectivity SoCs.
Bring up and debug large-scale models on Cadence Palladium, Zebu, or Veloce platforms.
Integrate SpeedBridge, VirtualBridge, Accelerated VIP, memory models, and custom transactors for PCIe, HBM4, Ethernet, AXI/AMBA, JTAG, and QSPI.
Develop HW/SW co-emulation and co-simulation flows using RTL, reference models, firmware, and software tests.
Build reusable transactors, agents, stubs, bridges, checkers, acceleration flows, and automation for regression triage and engineering productivity.
Optimize emulation speed and resource utilization, and develop LLM-based tools for log analysis, waveform triage, debug assistance, and flow generation.
Requirements
Strong hands-on experience with SoC emulation or system-level validation, including experience with at least one commercial emulation platform.
Working knowledge of Verilog/SystemVerilog and waveform debugging sufficient to develop custom transactors or agents; deep RTL design expertise is not required.
Strong Python and software automation skills, plus one or more of C, C++, Rust, Tcl, or shell.
Demonstrated ability to build tools and infrastructure rather than only run existing flows.
Strong system-level debugging across RTL, firmware, and software.
Ability to work independently and across architecture, RTL, DV, SoC, firmware, driver, kernel, validation, and EDA/vendor teams.
Nice to have
UVM or hybrid SoC testbench development and integration of cycle-accurate, software, or reference models into emulation/DV flows.
Rust verification or emulation experience, Bazel or large-scale build and regression systems, and reusable stimulus across simulation, emulation, and post-silicon.
AI/LLM experience building engineering tools beyond chat prompting.
Experience with connectivity SoCs, PCIe/CXL, Ethernet, DMA, HBM or memory subsystems, chiplets, or interconnect fabrics.
Firmware or driver bring-up on emulation platforms and scaling verification infrastructure across multiple projects or product lines.
Culture & Benefits
Full-time hybrid role with four weeks of accrued PTO, 12 company holidays, and up to three weeks of remote work.
Roth or pre-tax 401(k) with a 5% company contribution, professional development budget, and home-office setup support.
Onsite team meals, commute reimbursement, cell and internet reimbursements, and flexible employee perks.
Paid parental leave, pregnancy disability leave, flexible return-to-work hours, family support funding, and paid mental-health benefits.
Employment is contingent on the ability to perform the role in compliance with U.S. export control laws without obtaining an export-control license.
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