Senior Design Verification Engineer (SystemVerilog/UVM)

Location: Manila, Philippines. Full-time position. Requires satisfactory proof of the right to work in the Philippines and successful background and reference checks.

Company

hirify.global develops low-cost, low-power programmable logic, FPGA, CPLD, and programmable power management solutions for customers worldwide.

What you will do

• Draft design verification scope, strategy, and feasibility in response to marketing requirements.
• Develop verification test plans based on design specifications.
• Design and implement constrained-random testbenches and verification metrics.
• Code and execute tests, debug issues, and analyze results through closure.
• Collaborate through clear communication, documentation, and technical analysis.

Requirements

• BS or MS in Computer, Electronics, or Electrical Engineering with a minimum of 6 years of relevant design verification experience.
• Hands-on experience with SystemVerilog and UVM, including a solid understanding of available SV/UVM constructs.
• Experience with industry-standard digital design simulators and debugging tools.
• Good communication, collaboration, documentation, analysis, and debugging skills.
• Must provide satisfactory proof of the right to work in the Philippines.
• Successful background and reference checks are required.

Nice to have

• Experience with Python, Make, C, or C++.
• Understanding of HDL and FPGA concepts.
• Experience with Siemens EDA tools, Perforce, Git, Jenkins, or generative AI.
• Experience with cryptography, security, AMBA protocols, SPI, or I2C/I3C.

Culture & Benefits

• Work in a fast-paced, results-oriented, team-first environment.
• Collaborate within an international organization focused on R&D, product innovation, and customer service.
• Comprehensive compensation and benefits program is provided.
• Diversity of individuals, ideas, perspectives, insights, and values is recognized.