Staff Design Engineer (USB)

Location: Penang, Malaysia. Full-time position requiring satisfactory proof of the right to work in Malaysia.

Company

hirify.global develops low-cost, low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices.

What you will do

• Integrate USB controller and PHY IP into FPGA subsystems, including RTL, wrappers, adapters, clock/reset connectivity, configuration paths, and interfaces.
• Define subsystem RTL and integration specifications, and collaborate with Design Verification teams on simulation, emulation, FPGA prototyping, coverage closure, and pre-silicon debug.
• Drive root-cause analysis across controller-to-PHY interaction, integration RTL, software configuration, interoperability, compliance, and silicon behavior.
• Work with software, firmware, Design, DV, Applications, and external IP partners on USB enablement, diagnostics, enumeration, initialization, and user flows.
• Integrate DFT and DFD requirements and support silicon bring-up, laboratory debug, protocol analysis, compliance testing, customer issue resolution, and production-test considerations.
• Identify, develop, and deploy practical AI-assisted workflows for design, verification, debug, data analysis, and technical documentation.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
• Typically 8+ years of semiconductor, ASIC, SoC, or FPGA design experience.
• Strong RTL design and subsystem integration experience, including clock/reset architecture, configuration interfaces, timing, and CDC/RDC considerations.
• Strong experience with USB 2.0 or USB 3.x controllers, protocols, subsystem integration, or related USB PHY technology.
• Experience collaborating with Design Verification teams and debugging pre-silicon integration issues using simulation, emulation, or FPGA prototyping.
• Experience with silicon bring-up, laboratory debug, interoperability, or customer issue resolution.
• Experience with DFT or DFD methodologies, including testability, debug observability, scan/ATPG, silicon bring-up, or production-test considerations.
• Demonstrated experience identifying, proposing, developing, and implementing AI-assisted engineering workflows for design, integration, investigation, debug, data analysis, and documentation.
• Strong technical communication and collaboration skills across engineering disciplines.

Nice to have

• USB protocol debugging experience covering enumeration, link-state transitions, power management, error recovery, compliance, or interoperability testing.
• Experience with UTMI/UTMI+, ULPI, PIPE, or related USB controller-to-PHY interfaces.
• Experience with SerDes-based protocols or high-speed serial interfaces, including link bring-up and system-level debug.
• Understanding of USB PHY and mixed-signal behavior, including clocking, calibration, termination, equalization, jitter, reset sequencing, power management, initialization, and bring-up; direct analog circuit design experience is not required.
• Experience integrating third-party USB IP and working with external IP suppliers.
• Familiarity with synthesis, LEC, static timing analysis, timing closure, Lint, CDC, RDC, low-power/UPF, firmware, device configuration, APIs, scripts, drivers, or FPGA software-tool enablement.
• Exposure to USB compliance, interoperability, package, board, signal-integrity, connector, or platform-level considerations.

Culture & Benefits

• Work in an international, results-oriented engineering organization focused on R&D, product innovation, and customer service.
• Collaborate across a global workforce of approximately 1,000 employees.
• Comprehensive compensation and benefits program.
• Employment is conditional on successful background and reference checks.