Principal / Senior Principal Design Verification Engineer (CXL / PCIe / Ethernet)

Location: Taipei, Taiwan

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and software for hyperscalers and ecosystem partners.

What you will do

• Lead verification strategy for complex connectivity IPs and SoC subsystems from architecture through silicon.
• Define reusable verification methodologies, frameworks, coverage plans, regression processes, and sign-off criteria.
• Architect scalable UVM/SystemVerilog environments with scoreboards, protocol monitors, checkers, SVA assertions, and functional coverage models.
• Verify CXL, PCIe, Ethernet, AXI, APB, AHB, SerDes, and memory interfaces.
• Debug RTL, protocol, timing, simulation, and integration issues while supporting silicon bring-up and customer issue analysis.
• Mentor verification engineers and coordinate execution with architecture, RTL, firmware, emulation, FPGA, validation, and system engineering teams.

Requirements

• Bachelor’s or master’s degree in electrical, electronics, computer engineering, or a related field.
• 10+ years of design verification experience for Principal level or 15+ years for Senior Principal level.
• Strong expertise in SystemVerilog, UVM, constrained-random verification, coverage-driven methodologies, SVA, and functional coverage.
• Extensive experience with verification planning, execution, sign-off, protocol compliance, RTL debugging, waveform analysis, and simulation.
• Experience with Synopsys VCS, Cadence Xcelium, Siemens Questa, or comparable industry-standard simulators.
• Experience leading verification for large SoCs or complex connectivity IPs and delivering first-pass silicon programs.

Nice to have

• Expertise in CXL cache, memory, and I/O protocols; PCIe transaction, data link, and physical layers; or Ethernet MAC/PCS/PMA architecture.
• Experience with coherency protocols, high-speed interconnects, AI accelerator connectivity, data center SoCs, multi-chip systems, or chiplets.
• Knowledge of performance, low-power, CDC/RDC, formal, or Portable Stimulus verification.
• Experience with Python, Perl, Tcl, emulation, FPGA prototyping, or customer-facing post-silicon debug.

Culture & Benefits

• Collaborate with geographically distributed teams across architecture, design, firmware, validation, and system engineering.
• Drive engineering excellence, verification productivity, reusable infrastructure, and continuous improvement.
• The role may be eligible for discretionary bonuses, incentives, and benefits.
• Contribute to an inclusive environment that values diverse ideas, backgrounds, and experiences.