Principal Digital Design Engineer (PCIe)

Location: Taipei, Taiwan

Company

hirify.global develops rack-scale AI infrastructure and semiconductor-based connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies with its COSMOS software suite.

What you will do

• Define micro-architectures and implement complex digital blocks and subsystems.
• Own block-level design from architecture through GDS, including RTL coding, simulation, synthesis, and production delivery.
• Collaborate with verification teams on test plans, coverage closure, and complex debug.
• Drive timing closure, gate-level simulation, and Design-for-Test implementation.
• Support silicon bring-up, failure analysis, and post-silicon debug.
• Mentor junior engineers and improve silicon development processes.

Requirements

• Bachelor’s degree in electrical engineering or equivalent.
• 8+ years of hands-on experience developing complex SoC or silicon products in server, storage, and/or networking markets.
• Experience with advanced CMOS nodes of 7nm or smaller.
• Deep expertise in at least one high-speed protocol such as PCIe, Ethernet, InfiniBand, or DDR.
• Proficiency with Cadence and/or Synopsys digital design flows and familiarity with UVM-based verification.
• Experience with silicon bring-up, debug, failure analysis, and cross-functional collaboration.

Nice to have

• Experience delivering multiple high-performance designs to production in data-center environments.
• Collaboration with embedded firmware teams and familiarity with RISC-V, Arm, or similar processor subsystems.
• Contributions to design methodology, CAD automation, or design infrastructure.

Culture & Benefits

• Collaborative environment involving verification, physical design, DFT, post-silicon, and global teams.
• Opportunity to work on next-generation high-performance connectivity products.
• Inclusive workplace encouraging applications from people with diverse backgrounds and experiences.