Senior Software Engineer - Low Power Verification (UPF)

Location: Zhubei, Taiwan

Company

hirify.global develops technology for electronic design and verification, including Palladium and Protium emulation and prototyping platforms.

What you will do

• Improve the performance and correctness of UPF waveform generation across Parallel Partition Compiler and Modular Compiler flows, including Dielet UPF support.
• Improve SAGE-based UPF debugging with Verisium for better performance and usability.
• Develop AI-assisted, Verisium-integrated UPF debugging tools to reduce time to root cause for low-power design issues.
• Deploy UPF solutions across AVIP, UVMA, Modular Compiler, and Dielet flows supporting two-state and four-state UPF.
• Consolidate and unify UPF debugging across Palladium and Protium.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 4+ years of experience; master’s degree with 2+ years; PhD with 1+ year; or equivalent practical experience.
• Working knowledge of IEEE 1801 UPF and RTL languages including Verilog, SystemVerilog, and VHDL.
• Strong debugging and root-cause analysis skills using logs, waveforms, traces, testcases, and user reports.
• Ability to read, review, and reason about C++ code and object-oriented designs.
• Scripting experience with Perl, Tcl/Tk, and/or Python.
• Fluency with AI-assisted coding tools such as Copilot, Claude, Cursor, or equivalent, including critical evaluation of AI output.

Culture & Benefits

• Work on low-power verification software for next-generation emulation and prototyping platforms.
• Collaborate with R&D, PE, and AE teams.
• Contribute to technology intended to solve complex electronic design and verification challenges.