1 день назад
Experienced RTL Design Engineer (Semiconductor)
Вакансия из Hirify Global, списка международных tech-компанийДля мэтча и отклика нужен Plus
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Experienced RTL Design Engineer (Semiconductor): Designing and integrating PAD/PFC logic for SoC products with an accent on pin multiplexing, boundary scan, I/O control logic, and signoff quality. Focus on resolving lint, CDC, synthesis, timing, and formal verification issues, while automating design flows with Python and Tcl.
Location: Ho Chi Minh, Vietnam; onsite — remote work is not available
Employment: Full-time, regular permanent position.
Company
is an embedded semiconductor solution provider developing technology for automotive, industrial, infrastructure, and IoT applications.
What you will do
- Design and implement PAD/PFC logic for SoC products, including pin multiplexing, boundary scan, test functions, and I/O control logic.
- Implement PAD logic from design specifications, pinmux definitions, PAD-RTL/PAD-IO requirements, and integration guidelines.
- Generate, integrate, and validate PAD logic using in-house design tools and methodologies.
- Analyze and resolve issues identified by RTL lint, CDC, synthesis, timing, and formal verification tools.
- Develop Python and Tcl automation scripts to improve design productivity and flow efficiency.
- Collaborate with verification, DFT, STA, backend, and architecture teams through integration and signoff.
Requirements
- At least 3 years of experience in RTL design using Verilog/SystemVerilog.
- Understanding of digital design fundamentals, pin multiplexing, and I/O control logic.
- Good Python scripting skills; ability to work with in-house design tools.
- Experience with SpyGlass Lint and CDC, Genus/DC synthesis, and PrimeTime timing analysis.
- Ability to review verification, formal verification, and signoff results and resolve design issues.
- Strong problem-solving, communication, collaboration, self-learning, and ownership skills.
Nice to have
- Tcl knowledge.
- Experience with formal verification tools such as JG-CONN, JG-CSV, or JG-FPV.
- Basic understanding of DFT, boundary scan, and backend implementation.
Culture & Benefits
- Global organization with more than 21,000 engineers and problem solvers across over 30 countries.
- Culture based on being Transparent, Agile, Global, Innovative, and Entrepreneurial.
- Competitive benefits package provided alongside salary.
- Equal opportunity workplace committed to diversity and inclusion.
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