4 дня назад
Lead Design Engineer (SoC)
Вакансия из Hirify Global, списка международных tech-компанийДля мэтча и отклика нужен Plus
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Lead Design Engineer (SoC): Leading the design and integration of complex SoC, subsystem, and IP blocks from architecture interpretation through RTL delivery and design closure with an accent on micro-architecture, Verilog/SystemVerilog development, and cross-functional hardware integration. Focus on resolving timing, power, area, interface, and functionality issues, supporting verification and design-quality checks, and mentoring engineers across large SoC programs.
Location: Hyderabad, India; onsite
Company
develops technology solutions and supports leaders and innovators working on complex semiconductor and digital design challenges.
What you will do
- Lead end-to-end RTL design and development for SoC, subsystem, and IP blocks.
- Translate architecture and product requirements into micro-architecture and implementation plans.
- Design and integrate interconnects, controllers, bridges, memory interfaces, datapaths, and control logic.
- Coordinate with verification, physical design, DFT, firmware, and architecture teams to resolve interface, timing, power, area, and functionality issues.
- Drive lint, CDC, RDC, synthesis, low-power, formal, and design-closure activities.
- Mentor junior engineers and contribute to reusable IP, methodology, and automation improvements.
Requirements
- Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
- 10–14 years of digital design experience with strong exposure to IP, subsystem, and SoC development.
- Strong RTL design expertise using Verilog and SystemVerilog.
- Knowledge of digital design fundamentals, micro-architecture, FSMs, pipelines, arbitration, buffering, and clock/reset design.
- Experience with AMBA protocols including AXI, AHB, and APB, plus interconnects, DMA, memory-mapped peripherals, or protocol bridges.
- Scripting experience with Python, Perl, Tcl, or Shell, along with strong debugging and cross-functional collaboration skills.
Nice to have
- Experience with PCIe, DDR, NoC, cache/coherency, security, or safety-related designs.
- Exposure to UPF/CPF and low-power design methodologies.
- Formal verification support, silicon debug, or experience leading small design teams and major SoC subsystems.
Culture & Benefits
- Opportunity to work on complex technology and semiconductor design problems.
- Focus on technical leadership, design quality, reusable IP, and implementation-ready solutions.
- Full-time role with cross-functional collaboration across hardware development disciplines.
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