Staff Engineer - DFT (Semiconductor)

Location: Singapore

Company

hirify.global develops ultra-low-power semiconductor solutions for AI edge applications, wearables, medical devices, IoT products, and intelligent connected systems.

What you will do

• Implement scan insertion, boundary scan, MBIST, and ATPG for ultra-low-power SoCs.
• Develop low-power DFT architectures and infrastructure using standard EDA tools.
• Generate structural test vectors and improve test coverage, test time, and test cost.
• Run pre- and post-layout scan and MBIST simulations.
• Collaborate with design teams on timing, physical, power, and logical DFT-related issues.
• Work with test engineers to bring test vectors up on silicon and support production test development.

Requirements

• BS or MS in ECE or EE and at least 10 years of DFT implementation experience.
• Strong experience with scan structures, including stuck-at, at-speed, and path-delay testing, scan compression, boundary scan, and MBIST.
• Experience creating and implementing hierarchical DFT architectures for complex SoCs.
• Experience with low-power DFT, MBIST, scan ATPG, and pre/post-layout testbench simulation.
• Extensive knowledge of timing concepts, constraint development, RTL, and test coverage analysis.
• Strong verbal and written English communication skills.

Nice to have

• Experience with Tcl scripting.
• Experience with gate-level simulation.

Culture & Benefits

• Cross-functional work across semiconductor design, research, development, production, and test engineering.
• Complex technical work focused on energy efficiency and AI edge applications.
• Values include innovation, collaboration, focus, learning, and achievement.