Engineer II-Design

Location: PA - Allentown - Winchester Rd, United States; onsite

Company

hirify.global develops semiconductor products and SoC solutions with hard and soft IP blocks for imaging, networking, system connectivity, compute, and data storage.

What you will do

• Design RTL-based modules and create detailed design specifications.
• Analyze performance and implement RTL for ASIC and SoC designs.
• Perform synthesis, simulation, formal verification, and pre-layout/post-layout timing verification.
• Develop high-speed design techniques to improve bandwidth, reduce latency, and increase reliability.
• Support design porting to test chips and emulation platforms.
• Collaborate on FPGA design, board implementation, and system-level validation.

Requirements

• 2–5 years of experience in RTL design for ASIC implementation.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• Proficiency in SystemVerilog and experience with RTL design, synthesis, formal verification, RTL/gate-level simulation, cross-domain clocking analysis, and static timing analysis.
• Ability to design complex state machines and datapath logic and implement industry standards.
• Proficiency in TCL, Perl, or Python and Linux.
• Must provide proof of U.S. citizenship, permanent U.S. residency, or protected-individual classification under U.S. export-control requirements.

Nice to have

• Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• FPGA and ASIC SoC design experience.
• Laboratory experience in system-level validation.

Culture & Benefits

• Full-time employment within a large global semiconductor organization.
• Access to employee development and leadership programs.
• Work is performed 100% indoors, primarily seated, with 0–25% travel.
• Equal opportunity and affirmative action employment environment.