Founding Member of the Technical Staff (AI)

Location: On-site in Palo Alto, California, United States

Company

hirify.global is a frontier AI lab developing models and tools for on-demand custom ASIC design, verification, and exploration.

What you will do

• Co-design and implement reinforcement learning environments, algorithms, reward models, and reward signal experiments.
• Develop and scale post-training techniques for AI models used in production chip design.
• Build robust pipelines for model fine-tuning and evaluation.
• Own the end-to-end reinforcement learning workflow, from environment design and reward modeling to test-time optimization and scaling.
• Collaborate with research teams to productionize emerging techniques and debug complex training and model-behavior issues.

Requirements

• PhD in Computer Science, Computer Engineering, EECS, Mathematics, or a related field, or a BS/MS with strong research engineering experience.
• Deep expertise in reinforcement learning and post-training, with experience taking models from research to real-world deployment.
• Experience building end-to-end machine learning pipelines and fine-tuning LLMs or code models for reasoning, tool use, and structured coding tasks.
• Strong software engineering skills with experience in large-scale distributed systems, high-performance computing, and distributed training frameworks such as PyTorch, CUDA, QLoRA, or ZeRO.
• Ability to analyze and debug model training processes while maintaining engineering rigor and operational reliability.

Nice to have

• Experience on the post-training team at a frontier AI lab.
• Background in electrical or computer engineering, computer architecture, chip design, or verification.
• Publications in leading ML or EDA venues.
• Experience as a founding ML engineer, researcher, or early hire at an AI deep-tech startup.

Culture & Benefits

• Competitive salary and meaningful equity stake.
• Fast-paced startup environment with autonomy and visible impact.
• Opportunity to work on cutting-edge AI-driven chip design challenges.
• Hands-on ownership of a 0-to-1 technical area connecting fundamental research with production engineering.