Lead Debug/Trace/Profiling Design Engineer (RISC-V)

Location: La Ciotat, France. Right to work in France is required. Access to export-controlled technology is subject to authorization or successful export licensing.

Company

hirify.global develops configurable RISC-V processor cores and compute platforms for applications including artificial intelligence, machine learning, automotive, data centers, mobile, and consumer products.

What you will do

• Architect, design, and implement debug, trace, and profiling hardware for RISC-V processor subsystems.
• Collaborate with architecture, performance, software, and hardware teams on architecture and microarchitecture exploration and specifications.
• Implement configurable RTL generators and integrate new design content into the Chisel/FIRRTL framework.
• Improve automatic generation of documentation, verification testbenches, tests, and packaged software.
• Perform initial sandbox verification and work with the design verification team on comprehensive verification plans and execution.
• Engage with customers, partners, tools vendors, and RISC-V International on future debug, trace, and profiling capabilities.

Requirements

• 7+ years of industry experience leading and contributing to architecture, microarchitecture, and RTL design for debug, trace, or profiling hardware in high-performance processors.
• Knowledge of debug, trace, and profiling architectures, debug interfaces, JTAG, and cJTAG.
• Knowledge of CPU architectures, power management, and SoC design, including debugging tools and profiling methods.
• Proficiency in RTL design with Verilog, SystemVerilog, or VHDL.
• Knowledge of at least one object-oriented or functional programming language.
• MS or PhD in electrical engineering, computer engineering, computer science, or a related technical discipline.

Nice to have

• Experience with Chisel/Scala, RISC-V architecture, Git, Jira, or Confluence.

Culture & Benefits

• Full-time employment in a collaborative engineering environment.
• Work on configurable hardware generators designed for fast time-to-market and high-quality processor IP.
• Opportunities to contribute to open RISC-V and TileLink architectures and collaborate across product lines.
• Employment is contingent on successful background and reference checks.
• Equal opportunity workplace committed to diversity and inclusion.