Senior Principal Hardware Emulation Engineer (AI Hardware)

Location: San Jose, California, United States

Base salary: $210,000–$280,000 USD per year, plus equity and benefits.

Company

hirify.global develops a full-stack generative AI platform combining the SN40L chip, software, and open-source models for enterprise and government organizations.

What you will do

• Build high-performance emulation models for each new Reconfigurable Dataflow Unit generation using SystemVerilog and C/C++.
• Work with RTL design teams to make designs emulation-ready, including vendor-model substitution and custom model development.
• Own emulation environment architecture, including build and runtime flows, partitioning, compilation, clocking, and memory configuration.
• Automate hardware testing through scheduling, regression launches, failure triage, and results reporting.
• Enable software bring-up, performance analysis, and accelerated functional verification before silicon.
• Lead emulation methodology, vendor relationships, platform capacity, and technical direction across design, verification, and software teams.

Requirements

• BS or MS in EE, CE, or CS with 10+ years of industry experience, including deep hands-on emulation work.
• Hands-on experience with industry-standard platforms such as Palladium, Veloce, or Zebu, including compile flows, partitioning, debugging, and performance tuning.
• Strong SystemVerilog and C/C++ skills for transactors, behavioral models, memory models, and co-emulation infrastructure.
• Experience taking an emulation platform through a full chip program from bring-up through tape-out.
• Experience with Python and shell automation for regression, scheduling, and triage workflows.
• Ability to debug across RTL, models, transactors, flows, and software, and provide technical leadership without formal authority.

Nice to have

• MS or PhD in EE, CE, or CS with 12+ years of experience.
• Depth with Cadence Palladium or multiple emulation platforms.
• Experience with machine learning accelerators, dataflow architectures, reconfigurable silicon, PCIe, Ethernet, HBM, or DDR.
• Experience with virtual or hybrid platforms, FPGA prototyping, post-silicon debug, compiler or runtime software, or AI tools for automation.

Culture & Benefits

• Full-time US employment with a competitive total rewards package including base salary, equity, and benefits.
• Medical insurance with 95% employee premium coverage and 77% dependent premium coverage.
• Health Savings Account with employer contribution, plus dental, vision, disability, life, AD&D, and flexible spending account options.
• Well-being benefits including Headspace, Gympass+, One Medical, counseling, and an Employee Assistance Program.

Hiring process

• Submit a separate application form for each position for which you are qualified.