ASIC Architect (AI)

TL;DR

ASIC Architect (AI): Defining and delivering next-generation compute architectures for an AI and semiconductor platform with an accent on system-level design, memory hierarchies, interconnects, and full ASIC execution. Focus on modeling performance and cost, guiding RTL, verification, physical integration, and packaging, and delivering silicon from concept through tape-out.

Location: Paris offices or remote from Europe; relocation support is available for moving within 20 minutes of the company location.

Company

hirify.global is an early-stage AI and computer hardware company developing advanced compute architectures at the intersection of artificial intelligence and semiconductors.

What you will do

• Define the top-level architecture of a multiphysics compute platform, including processing elements, interconnects, memory subsystems, and system-level control.
• Own architecture from concept through tape-out, including system modeling, specifications, and implementation handoff.
• Guide and mentor multidisciplinary teams across RTL design, functional verification, and physical integration.
• Collaborate with software, packaging, and system integration teams on platform scalability, performance, and reliability.
• Evaluate new architectural directions, build performance and cost models, and lead prototyping to reduce technical risk.

Requirements

• Proven experience architecting complex, high-performance digital systems such as multicore processors, vector engines, or domain-specific accelerators.
• Deep expertise in computer architecture, including memory hierarchies, interconnects, cache coherence, instruction set design, and performance-power-area trade-offs.
• Hands-on experience designing and integrating vector ALUs, SIMD pipelines, systolic arrays, or custom signal and tensor-processing datapaths.
• Experience leading complete ASIC development cycles from architectural concept and modeling through RTL, verification, physical design, and tape-out.
• Strong leadership and communication skills for aligning architecture, RTL, verification, software, and physical design teams.

Nice to have

• Experience with HBM, chiplets, and 2.5D/3D integration technologies and their system-level architectural impact.

Culture & Benefits

• Competitive cash compensation determined by location, experience, and internal compensation benchmarks.
• Meaningful stock options included in most full-time offers at this early stage.
• Relocation bonus and moving-expense coverage for relocation within 20 minutes of the company location.
• Healthcare coverage, including family-friendly options, pension contributions, professional development support, 25 days of paid time off, and public holidays.
• High-paced, multicultural, engineering-led environment with ownership of a key technical domain and opportunities for growth.