FPGA Engineer (ASIC Prototyping)

TL;DR

FPGA Engineer (ASIC Prototyping): Implementing ASIC designs on FPGA platforms for prototyping and validation with an accent on RTL integration, debugging, and timing analysis. Focus on developing FPGA-based prototype systems, resolving Static Timing Analysis (STA) issues, and enabling early hardware and software validation.

Location: On-site presence required in Petah-Tikva or Haifa, Israel

Company

hirify.global is a global leader in semiconductor design and manufacturing, driving advancements in the semiconductor industry to power worldwide technology innovations.

What you will do

• Implement ASIC designs on FPGA platforms for prototyping and validation.
• Develop and maintain FPGA-based prototype systems.
• Integrate, debug, and verify RTL designs in the FPGA environment.
• Collaborate with ASIC design, verification, and system teams to enable early hardware and software validation.
• Analyze prototype performance and resolve functional or timing issues.
• Support bring-up, testing, and deployment of FPGA prototype platforms.

Requirements

• Bachelor's in Electrical/Computer Engineering (3+ years exp), Master's (2+ years), or PhD.
• Experience with FPGA synthesis tools such as Altera Quartus and AMD (Xilinx) Vivado.
• Expertise in troubleshooting and solving Static Timing Analysis (STA) issues in FPGA designs.
• Experience with hardware simulation tools and RTL design.
• Strong debugging skills to root cause and resolve design and verification issues.
• Must be based in or able to work on-site in Israel.

Nice to have

• Familiarity with digital design fundamentals and hardware board design concepts.
• Familiarity with System Verilog for test bench creation and functional verification.
• Experience with Synplify Premier (Synopsys FPGA synthesis tool).
• Strong problem-solving skills and a results-oriented approach to execution.
• Experience in group problem solving within cross-functional teams.