Graduate Talent (Analog Layout Engineer)

TL;DR

Graduate Talent (Analog Layout Engineer): Executing custom layout implementation and physical verification for analog blocks in SoC and IP designs with an accent on layout constraints and reliability standards. Focus on performing DRC/LVS checks, supporting layout iterations, and collaborating with senior designers to ensure high-quality silicon implementation.

Location: Must be based in Penang or Kulim, Malaysia (Hybrid work model).

Company

hirify.global is a global leader in semiconductor technology, building scalable engineering solutions for product enablement, custom ASICs, and foundry services.

What you will do

• Perform analog and custom layout design for assigned blocks under senior supervision.
• Implement layouts using industry-standard tools like Virtuoso or Custom Compiler.
• Execute and debug physical verification checks including DRC, LVS, and density/reliability analysis.
• Run EM/IR, ESD, and Latch-up checks to ensure design robustness.
• Support layout iterations, ECOs, and signoff closure processes.
• Document layout issues and participate in technical reviews with senior engineering staff.

Requirements

• Bachelor's degree in Electrical or Electronics Engineering.
• 0-2 years of experience or strong academic exposure to Analog/Custom Layout Design.
• Basic understanding of analog layout practices, matching concepts, and reliability considerations.
• Familiarity with physical verification flows and custom layout tools.
• Ability to work as an individual contributor under technical guidance.
• Must be located in or able to work on-site in Penang or Kulim, Malaysia.

Culture & Benefits

• Hybrid work model allowing flexibility between on-site and off-site work.
• Opportunity to work within the Central Engineering Group on cutting-edge silicon projects.
• Mentorship from senior layout and circuit designers.
• Commitment to ethical hiring practices and RBA compliance.