Principal ASIC Physical Design Engineer

TL;DR

Principal ASIC Physical Design Engineer (ASIC): Lead the implementation of complex SoCs for next-generation satellite and space systems with an accent on full RTL-to-GDSII ownership, timing closure, and PPA optimization. Focus on driving sign-off across multi-corner/multi-voltage conditions, managing external physical design partners, and ensuring first-pass silicon success in advanced FinFET technologies.

Location: United States - Remote

Salary: $190,000–$280,000 + equity

Company

hirify.global builds high-power satellite platforms for missions from LEO to deep space.

What you will do

• Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, CTS, STA, physical verification (DRC/LVS), and sign-off.
• Develop and maintain physical design methodologies, scripts, and automation to optimize PPA (performance, power, area).
• Collaborate with architecture, RTL design, DFT, and packaging teams to ensure clean handoffs and efficient design iteration.
• Drive timing closure across multiple voltage and process corners and support sign-off with foundry-qualified tools.
• Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration.
• Manage and technically guide external physical design partners and work with EDA vendors to debug and optimize tool flows.

Requirements

• 10+ years of ASIC physical design experience for high-performance SoCs.
• Proven end-to-end RTL-to-GDSII expertise using industry tools (Synopsys, Cadence, or Siemens).
• Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
• Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
• Experience with advanced FinFET process nodes and DFT integration, STA sign-off, and power domain implementation (UPF/CPF).
• Ability to meet U.S. export compliance requirements (must be a “U.S. person” or eligible for a federally issued export control license).

Nice to have

• Exposure to radiation-hardened or space-qualified ASICs.
• Experience with chip-package co-design and advanced packaging (2.5D/3D).
• Experience driving tapeouts through TSMC and/or Gate-All-Around technologies.
• Experience working with geographically distributed teams and managing offshore/outsourced PD vendors.

Culture & Benefits

• Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, and paid parental leave.
• Equity included in compensation.
• Remote work based in the United States.
• Opportunity to support production and spaceflight for next-generation satellite systems.

Hiring process

• Application review with evaluation of end-to-end physical design ownership and timing closure experience.
• Interviews focused on technical depth, cross-functional collaboration, and leadership/mentoring.
• Export compliance eligibility check as part of the hiring process.