Middle RTL Engineer (Digital Design)

TL;DR

Middle RTL Engineer (Digital Design): Implement design microarchitecture at RTL level for high-performance blocks with an accent on RTL debugging, lint checks, and CDC analysis. Focus on ensuring design correctness, optimizing power for energy-efficient designs, and collaborating with verification and physical design teams.

Location: Remote or hybrid within Ukraine (Lviv, Kyiv, Rivne, Odesa)

Company

hirify.global Engineering is a global leader in engineering services providing R&D across various industries including automotive and robotics.

What you will do

• Implement design microarchitecture at RTL level for high-performance blocks based on functional specifications.
• Perform RTL debugging to ensure design correctness and efficiency.
• Run and analyze Lint and Clock Domain Crossing (CDC) checks.
• Apply power optimization techniques for energy-efficient designs.
• Collaborate with verification, physical design, and architecture teams.

Requirements

• 3+ years of hands-on experience in digital design.
• Strong knowledge of Verilog and/or VHDL for synthesis.
• Proven experience in RTL design, uArch development, and functional specifications.
• Basic understanding of linting tools, CDC methodologies, and debugging flows.
• Bachelor's degree in EE, ECE, CE, CS, or a related field.

Nice to have

• Familiarity with SystemVerilog.
• Experience with tools like Cadence Genus, Synopsys Design Compiler (DC), or Fusion Compiler.
• Experience working on SoC-level integration and design.
• Ability to contribute to Front-End Synthesis and optimization.
• Advanced degree (MS or PhD).

Culture & Benefits

• Health insurance provided from the first day of employment.
• Company-gifted Christmas holidays from December 25 to December 31.
• Active support for veterans and psychological rehabilitation via Superhumans and Veteran HUB.
• Inclusive and diverse global work environment.