Physical Design Engineer (ASIC)

TL;DR

Physical Design Engineer (ASIC): Driving the physical design backend block flow for state-of-the-art 5nm, 3nm, and 2nm ASIC projects with an accent on block-level place and route, timing analysis, and DRC/LVS verification. Focus on implementing high-performance physical designs for top-tier customers within a global semiconductor leader.

Location: Must be based in Bulgaria (Plovdiv, Varna, or Sofia)

Company

hirify.global is a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Drive the physical design backend block flow for advanced 5nm, 3nm, and 2nm ASIC projects.
• Perform block-level Place and Route.
• Conduct comprehensive timing analysis.
• Execute DRC/LVS verification to ensure design integrity.
• Collaborate with the ASIC physical design implementation team to deliver solutions for top-tier customers.

Requirements

• Junior-level experience in physical design.
• Strong understanding of ASIC physical design flows.
• Ability to work from hirify.global offices in Bulgaria (Plovdiv, Varna, or Sofia).