Senior Design Engineer (Semiconductor)

Location: Petah-Tikva, Israel; onsite

Salary: Competitive compensation

Company

hirify.global develops semiconductor solutions for enterprise, cloud, AI, and carrier data infrastructure.

What you will do

• Own one or more key digital blocks for next-generation network switches.
• Lead block design from architecture definition through RTL implementation.
• Optimize area, timing, and power across the design flow.
• Perform lint, CDC/RDC analysis, synthesis, timing closure, and backend-flow activities.
• Collaborate with verification engineers on block-level verification and alignment of design and verification goals.

Requirements

• B.Sc. or M.Sc. degree in Electrical Engineering.
• 5+ years of relevant digital design experience.
• Proficiency in RTL design using Verilog or SystemVerilog.
• Experience with linting, CDC/RDC analysis, synthesis, timing closure, power optimization, and backend flows.
• Strong problem-solving, analytical, collaboration, and communication skills.
• Eligibility to access technology and software subject to U.S. export control laws may be required; some applicants may undergo an export license review.

Nice to have

• Verification experience using SystemVerilog and UVM.
• Ability to quickly understand complex systems.

Culture & Benefits

• Competitive compensation and benefits.
• Collaborative, transparent, and inclusive work environment.
• Resources and support for professional growth and development.
• Interview participants may not use AI tools or automated assistance without prior instruction.