Physical Design Intern (ASIC)

Location: Cordoba, Argentina

Company

hirify.global develops semiconductor solutions that serve as building blocks for enterprise, cloud, AI, and carrier data infrastructure.

What you will do

• Implement tool flows, CAD methodologies, and scripts for ASIC physical design.
• Perform block-level layout implementation, place and route, synthesis, and physical synthesis.
• Conduct static timing, crosstalk, and design-for-testing analysis and complete timing closure.
• Optimize designs for timing, area, and power while learning advanced technology-node design rules.
• Document work and present and defend technical decisions and results.

Requirements

• Currently pursuing a degree in Electronic Engineering or a related technical field.
• Fewer than four final exams remaining, with a degree thesis in progress, or less than six months until graduation.
• Fluent spoken and written English.
• Good spoken and written Spanish.
• Thorough and detail-oriented approach.
• Eligibility to access export-controlled technology may be required, subject to U.S. export-control regulations and any applicable licensing review.

Nice to have

• Experience with circuit design using Synopsys, Cadence, or Mentor CAD tools.

Culture & Benefits

• Part-time position with training provided for all required skills.
• Collaborative, transparent, and inclusive work environment.
• Competitive compensation and benefits.
• Resources for professional development and career growth.

Hiring process

• Interviews assess individual experience, thought process, and communication skills in real time.
• AI tools, transcription apps, automated answer generators, and automated note-taking bots are not permitted during interviews.