Senior Design Verification Engineer (AI HW)

TL;DR

Senior Design Verification Engineer (AI HW): Validating compute IP and subsystems for AI-native architectures, including RISC-V CPUs and chiplet-based designs, with an accent on building scalable DV infrastructure and automated verification. Focus on coverage-driven verification, debugging complex RTL issues, and integrating CI/CD pipelines for production-grade hardware.

Location: Hybrid, based out of Toronto, ON or Austin, TX

Compensation: $100k - $500k (including base and variable compensation targets)

Company

hirify.global is developing a high-performance AI platform and RISC-V CPUs to revolutionize computing performance, ease of use, and cost efficiency.

What you will do

• Verify Tensix IP and subsystems from early planning through tape-out, owning and driving coverage goals to closure.
• Build and maintain reusable verification environments, agents, and scoreboards in SystemVerilog and Python.
• Develop constrained-random and directed tests to ensure functional, code, and assertion coverage.
• Debug complex issues across RTL and testbench in collaboration with design, firmware, compiler, and architecture teams.
• Evolve DV infrastructure, including regression flows, CI/CD integration, and EDA compute environments.

Requirements

• Experience in modern verification methodologies with strong SystemVerilog skills.
• Ability to perform block-level to system-level verification and reason about microarchitecture behavior via specs and waveforms.
• Proficiency in Linux environments with Python or Bash scripting for build automation and CI pipelines.
• Skill in coverage-driven verification and debugging across RTL and workload scenarios.
• Must be eligible to access U.S. export-controlled technology (compliance with EAR laws).

Culture & Benefits

• Work on cutting-edge AI-native compute architectures including matrix and vector units.
• Collaborative environment focused on solving hard technical problems.
• Highly competitive compensation package and benefits.
• Opportunity to work with advanced numerical precision formats (BF16, FP4, INT8) and scalable DV infrastructure.