Design Verification Engineer (SystemVerilog/UVM/DDR)

TL;DR

Design Verification Engineer (SystemVerilog/UVM/DDR): Developing and maintaining UVM-based verification environments for digital IP and SoC designs with an accent on DDR protocols and high-performance semiconductor products. Focus on creating detailed test plans, debugging complex design issues, and ensuring high-quality coverage closure.

Location: Onsite in Belgrade, Nis, or Novi Sad, Serbia

Company

hirify.global is a global leader in consulting, technology services, and digital transformation, providing specialized engineering services for next-generation semiconductor products.

What you will do

• Develop and maintain UVM-based verification environments for digital IP and subsystems.
• Create detailed test plans, testbench components, sequences, and functional coverage models.
• Execute verification at block, subsystem, and system levels.
• Debug design and verification issues using waveform viewers and simulation tools.
• Collaborate with architects and designers to review specifications and identify corner cases.
• Verify and validate DDR memory controller or PHY interfaces to ensure compliance with standards.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of hands-on experience in ASIC/FPGA design verification.
• Strong proficiency in SystemVerilog and UVM methodology.
• Proven experience with DDR protocol verification (DDR3, DDR4, LPDDR4/5, or DDR5).
• Proficiency with simulation, regression, and debugging tools such as VCS, Questa, or Incisive.
• Excellent problem-solving and communication skills.

Culture & Benefits

• Permanent employment contract.
• Opportunity to work on next-generation semiconductor products.
• Collaborative environment working closely with architects and design teams.
• Professional growth within a large-scale global technology organization.