SoC Power Architecture Engineer (AI)

TL;DR

SoC Power Architecture Engineer (AI): Defining and owning the power and voltage domain architecture for high-performance HPC-class silicon with an accent on system-level power efficiency and thermal constraints. Focus on designing complex power domains, DVFS implementation, and ensuring architectural trade-offs across chiplet-based SoC designs.

Location: Seongnam, South Korea (Onsite)

Company

hirify.global is an AI semiconductor company specializing in high-performance hardware solutions for AI workloads.

What you will do

• Define system-level power and voltage domain architecture for HPC SoCs with large power envelopes.
• Design power domains including retention, switchable, and always-on structures to support DVFS and performance state scaling.
• Manage the interactions between on-chip power management logic and external PMICs or board-level delivery ICs.
• Lead architectural trade-offs considering power density, thermal limits, performance, and cost.
• Provide technical guidance to design engineers during the exploration phase.

Requirements

• Master’s or higher degree in Electrical Engineering, Computer Science, or related field.
• Minimum of 5 years of professional experience in SoC or large-scale system power architecture.
• Comprehensive understanding of voltage and power domain design, power sequencing, and DVFS in complex systems.
• Technical proficiency in performance scaling and power domain interactions.

Hiring process

• Document screening followed by an online interview.
• On-site interview and culture-fit assessment.
• Final compensation negotiation and offer.