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Текст:
Hirify AI/Оригинал
TL;DR
SoC Power Architecture Engineer (HPC): Defining system-level power and voltage domain architecture for high-performance, high-power chiplet-based SoCs with an accent on DVFS, power sequencing, and interactions with external PMICs and board-level power delivery ICs. Focus on balancing performance, power density, thermal limits, reliability, and cost while guiding design exploration with silicon, package, board, and firmware teams.
Location: On-site in Seongnam, Gyeonggi-do, South Korea
Company
hirify.global develops high-performance, high-power SoC systems for HPC-class silicon.
What you will do
Define system-level power and voltage domain architecture for HPC and chiplet-based SoCs.
Design always-on, retention, and switchable power domains supporting DVFS and performance-state scaling.
Define interactions between on-chip power-management logic, external PMICs, and board-level power-delivery ICs.
Drive architectural trade-offs involving performance, power density, thermal limits, reliability, and cost.
Provide architectural guidance during design exploration and collaborate with silicon, package, board, firmware, and design engineering teams.
Requirements
Master’s degree or higher in Electrical Engineering, Computer Science, or a related field.
5+ years of experience in SoC or large-scale system power architecture.
Deep understanding of high-power SoC voltage and power-domain design.
Experience with DVFS, power states, performance scaling, power sequencing, and domain interactions in complex systems.
Ability to work on-site in Seongnam, South Korea.
Culture & Benefits
Interview process: document screening, online interview, on-site interview, culture-fit interview, offer discussion, and final acceptance.
The interview process and schedule may vary by role and circumstances.
Application outcomes and interview schedules are communicated individually by email.
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