Lead Application Engineer (Timing Analysis)

TL;DR

Lead Application Engineer (Timing Analysis): Provide technical support and validation for signoff timing analysis tools in advanced semiconductor SoC projects with an accent on timing optimization, regression testing, and tool integration. Focus on solving complex timing issues, enhancing timing analysis mechanisms, and supporting customers in digital design flows.

Location: Grenoble, France (onsite)

Company

hirify.global hires and develops leaders and innovators impacting the world of technology, specializing in semiconductor design tools and solutions.

What you will do

• Validate new tool releases through regression testing and coordinate tool versions.
• Enhance timing analysis mechanisms for advanced technology nodes.
• Investigate and resolve complex timing issues including algorithmic and physical phenomena.
• Write and maintain timing constraints; perform cross-domain clock checking for signoff validation.
• Support customers in timing optimization setup, ECO flows, and tool usage on live projects.
• Collaborate with hirify.global R&D and customer design teams on tool qualification and integration.

Requirements

• Must have 4 to 10 years experience in digital design flow and timing analysis.
• Fluent in English; French is a plus.
• Good knowledge of Static Timing Analysis (STA) and signoff methodologies.
• Experience with digital implementation flows, timing optimization, SDC and CDC checks.
• Working knowledge of UNIX/Linux and scripting languages (C-shell, TCL/TK, Python).
• Exposure to AI/ML techniques and interest in applying them for design optimization or predictive analysis.
• Degree in Electrical/Electronic Engineering, Microelectronics, or related discipline.

Culture & Benefits

• Work on challenging and impactful semiconductor SoC projects.
• Collaborate with leading companies and internal R&D teams.
• Opportunity to apply AI/ML in design optimization.