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3 дня назад

Lead Design Engineer

Π€ΠΎΡ€ΠΌΠ°Ρ‚ Ρ€Π°Π±ΠΎΡ‚Ρ‹
hybrid
Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
lead
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
Poland
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

ОписаниС вакансии

ВСкст:
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TL;DR

Lead Design Engineer (Embedded_IoT_Dev): Leading digital design verification for complex IP blocks with an accent on verification planning, SystemVerilog/UVM environment architecture, and coverage closure. Focus on designing verification methodologies, debugging, and mentoring engineers to ensure sign-off readiness.

Location: Must be legally eligible to work in Poland; office-based/hybrid in Warsaw

Company

hirify.global is a leader in electronic design software and hardware, serving innovative companies in consumer, hyperscale computing, 5G, automotive, aerospace, industrial, and health markets.

What you will do

  • Lead digital design verification architecture and verification plans for complex IP blocks.
  • Architect and implement SystemVerilog/UVM-based verification environments and assertions.
  • Drive functional coverage definition, analysis, and closure.
  • Perform debug and root-cause analysis across RTL, testbench, and simulation results.
  • Mentor junior verification engineers and influence verification methodologies.
  • Collaborate with design, architecture, and cross-site teams.

Requirements

  • 7+ years experience in digital design verification or semiconductor IP development.
  • Strong hands-on experience with SystemVerilog, UVM, and assertion-based verification (SVA).
  • Fluent English and effective communication skills for distributed/remote teams.
  • Legal eligibility to work in Poland.
  • Strong debugging, analytical, and problem-solving skills.
  • Working knowledge of UNIX/Linux, scripting, and automation.

Nice to have

  • Experience with metric-driven verification and sign-off methodologies.
  • Exposure to formal verification, low-power, CDC, or lint flows.
  • Knowledge of processor-based systems and embedded software interaction.
  • Semiconductor IP development or FPGA design experience.
  • Familiarity with industry-standard protocols (PCIe, CXL, AMBA, AXI, USB).
  • Understanding of cryptographic algorithms and security-related verification.

Culture & Benefits

  • Competitive salary with copyrights tax relief.
  • Flexible working hours and hybrid work model.
  • Continuous professional development through trainings and seminars.
  • Employee Stock Purchase Plan, bonuses, and stock programs.
  • Private medical care, life insurance, and Multisport Plus cards.
  • Social Fund benefits and opportunity to work for a Fortune 100 organization.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’

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